Other Parts Discussed in Thread: ADC12DJ3200
I want to know whether TI has a System Verilog model of the ADC12dj3200qml-sp ADC. I want to use it for simulating my FPGA interface. All I require is the JESD204B interface section with the sampling of data to put into the JESD lanes. Thus something I can just select the JMODE and provide data samples, either randomly generated or sequential or read from file or any method to input data into the JESD interface model.