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ADS1256: SCLK write timing

Hiroaki Yuyama TED
Expert 1740 points
Part Number: ADS1256

Dear, support Team.

We are having trouble writing SCLK to the ADS1256.
Our SCLK starts HI, not LO.
This is controlled by an LSI separate from the SPI interface.
For example, can reset timing using SCLK be reset without the rising edge of SCLK?

Best Regards,
Hiroaki Yuyama

  • 0
    TI__Guru 52626 points

    Hi Hiroaki Yuyama,

    The ADS1256 requires the clock to idle low, not high, otherwise the ADC will not function properly.

    You will need to configure the controller to SPI mode 01 (clock idles low, data on DIN is shifted into the part on the falling edge of SCLK while data is shifted out on DOUT on the rising edge of SCLK)

    -Bryan

  • 0 in reply to Bryan Lizon86
    Expert 1740 points

    HI Bryan-san,

    Thank you for your reply.
    I understand that starting our SCLK HI is problematic.
    We will set the controller to SPI mode 01.

    Best Regards,
    Hiroaki Yuyama

  • 0 in reply to Hiroaki Yuyama TED
    TI__Guru 52626 points

    Sounds good Hiroaki Yuyama, let us know if you need anything else

    -Bryan

  • 0 in reply to Bryan Lizon86
    Expert 1740 points

    HI Bryan-san,

    Thank you for your Help.
    When accessing (read/write) the ADS1256, the clock is idle low just before CS is brought low, and the data sheet
    I have followed the timing diagrams posted.


    In our LSI, CPOL = 1 (clock is idle high), so can't we connect it to the same SPI as the ADS1256?
    t3 CS low to first SCLK: Is it OK to go high when the clock is idle if I observe setup time and t10 CS low after final SCLK falling edge?
    We asked for confirmation.

    Best Regards,
    Hiroaki Yuyama

  • 0 in reply to Hiroaki Yuyama TED
    TI__Guru 52626 points

    Hi Hiroaki Yuyama,

    Hiroaki Yuyama TED said:
    In our LSI, CPOL = 1 (clock is idle high), so can't we connect it to the same SPI as the ADS1256?

    Yes, this is correct. The ADS1256 requires that CPOL = 0

    Hiroaki Yuyama TED said:
    t3 CS low to first SCLK: Is it OK to go high when the clock is idle if I observe setup time and t10 CS low after final SCLK falling edge?

    Can you please explain what you mean by "is it OK to go high when the clock is idle"? Are you asking if CS can be brought high when the clock is idle? You should follow the SPI frame sequence and timing as shown in Figure 1 in the ADS1256 datasheet.

    -Bryan

  • 0 in reply to Bryan Lizon86
    Expert 1740 points

    HI Bryan-san,

    Thank you for your Reply.
    I have an additional question, is there no problem if SCLK is Hi when CS=Hi?

    Also, when CS=Lo, t3 CS to first SCLK low: Observing the setup time and t10 SCLK falling edge, is it OK for SCLK to go high when the clock is idle?
    "When CS is Lo, follow the timing chart in Figure 1 of the data sheet."
    In our LSI, when CS is Hi, SCLK becomes Hi.

    Best Regards,
    Hiroaki Yuyama

  • 0 in reply to Hiroaki Yuyama TED
    TI__Guru 52626 points

    Hi Hiroaki Yuyama,

    The clock polarity (CPOL) bit is defined during the "idle state". The "idle state" is defined as the period when CS is high and transitioning to low at the start of the transmission and when CS is low and transitioning to high at the end of the transmission.

    Therefore, SCLK must be low slightly before CS is toggled low, and CS must also be low slightly after CS is brought high. I would strongly encourage you to use the correct CPOL setting for the ADS1256 so the ADC performs as expected

    -Bryan

  • 0 in reply to Bryan Lizon86
    Expert 1740 points

    HI Bryan-san,

    Thank you for your advice.
    We try to use CPOL=0 as much as possible.
    Since the ADS1256 can also be reset by SCLK, is that also why you recommend CPOL=0 ?
    We instruct the designer who designed the LSI circuit to make changes.

    Best Regards,
    Hiroaki Yuyama

  • 0 in reply to Hiroaki Yuyama TED
    TI__Guru 52626 points

    Hi Hiroaki Yuyama,

    You are correct that the ADS1256 can be reset using the SCLK pin only. However, this type of RESET requires a very specific pattern on SCLK, so I don't think this is the issue.

    The main issue is that the ADC is expecting SCLK to idle low for the entire duration of the communication frame, including some time before and after. Is there some reason why you cannot set CPOL = 0 in your system? Do you have other devices on the SPI bus where CPOL = 1?

    -Bryan

  • 0 in reply to Bryan Lizon86
    Expert 1740 points

    HI Bryan-san,

    Thank you for your reply.
    We decided to change the ADS1256 interface from LSI to a microcontroller that can set CPOL = 0.
    This is our feedback.
    Thank you very much!

    Best Regards,
    Hiroaki Yuyama

  • 0 in reply to Hiroaki Yuyama TED
    TI__Guru 52626 points

    Hi Hiroaki Yuyama,

    I am glad you could resolve this issue.

    If you need additional help, please start a new thread and we will support you there

    -Bryan