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LM98640QML-SP: Sample Rate

Ray Vincent Aranzaso
Mastermind 18180 points
Part Number: LM98640QML-SP

Hi,

Good Day.

The LM98640QML-SP datasheet states a sample rate range from 5-MSPS to 40-MSPS. Our customer would like to use readout rates as low as 1 MSPS to reduce readout noise. Is there a limitation that does not allow the chip to sample this slowly?

 

"I took the previous response to mean that performance was not guaranteed at lower clock rates. Not that we are detailing the design I am trying to figure out how to configure the INCLK Range for lower rates. If this is not possible, please let me know as we need to pivot if lower rates are impossible."

Please advise. Thank you very much.

Best Regards,

Ray Vincent

  • 0
    TI__Expert 4890 points

    Hi Ray, 

    Unfortunately, the minimum INCLK supported for this part is 5MHz.

    But the customer should still be able to use this device (at 5MHz) for a pixel rate of 1MHz by setting it in Sample and Hold mode (Osx- ac-coupled to CCD sensor output, Osx+ connected to VCLP and a 0.1uF capacitor to ground) as shown in Figure 29 in the datasheet. Then, the ADC running at 5MHz essentially captures 5 samples per pixel (S1-S5) - S1,S2 can be pedestal value, S3 can be ignored, and S4, S5 can be the data. Then, a CDS can be performed in digital as: (S4+S5)/2 - (S1+S2)/2 to cancel the reset noise. In this method, the noise from the device will still be 79dB on 2V (=224 uVrms) at 1x gain. 

    The customer should also use the clamp mode (section 7.3.2 and 7.3.2.1 in datasheet) by periodically and appropriately applying CLPIN signal to set the DC-voltage across the input coupling caps (highlighted in Figure 29 above). 

    Let me know if customer has more questions on this. 

    Thanks,

    Karthik

  • 0 in reply to Karthik Nagabhushana
    TI__Mastermind 18180 points

    Hi Karthik,

    Good Day. Can we switch between this sample and hold techniques and correlated double sampling with the same physical configuration (no difference in how pins and caps are connected) so we can provide readout up to 25 MSPS?

    Please advise. Thank you very much.

    Best Regards,

    Ray Vincent

  • 0 in reply to Ray Vincent Aranzaso
    TI__Expert 4890 points

    Hi Ray, 

    I need some time to analyze this request. I will get back to you by tomorrow. 

    Thanks for your patience. 

    Karthik

  • 0 in reply to Karthik Nagabhushana
    TI__Expert 4890 points

    Hi Ray, 

    A small hardware modification would be required to switch between Sample-Hold mode and CDS mode. 

    In CDS Mode, the OSX+ pins should each be decoupled with 0.1-μF capacitors to ground. So, OSX+ must not be connected to VCLP as shown in Figure 29. 

    Thanks,

    Karthik