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FMC-ADC-ADAPTER: FPGA Clock input from Zynq 7000 to ADC3444EVM

Alireza Ranjbar
Prodigy 10 points
Part Number: FMC-ADC-ADAPTER
Other Parts Discussed in Thread: ADC3444, , ADC3444EVM, LMX2572LP

Hello,

I am currently using the ADC3444EVM for my project. I would like to connect my Zynq-7000 FPGA to the EVM board via the FMC-ADC-Adapter. I am a beginner and this is my first time working with an ADC and as I understand the ADC3444EVM requires a clock input through pin J9 (SMA port). I would like to send the clock input from my FPGA to the EVM board. Taking a look at the schematic of the FMC-ADC-Adapter and ADC3444EVM, it shows a pin called the "SCLK" that connects from the FMC on the FMC-ADC-Adapter to the SCLK pin of the ADC3444. Can I use this SCLK pin to send a clock input rather than the SMA port, pin J9? Or is pin J9 of the ADC3444EVM the only way to send the ADC3444 a clock input? If so, do you have any ideas how I could still use my FPGA to send a clock input to the J9 pin (SMA port)? Perhaps a self-designed PCB connected to the FPGA with a SMA port connecting to the EVM SMA J9 pin.

Thank you and best regards,

Alireza

  • +1
    TI__Mastermind 22060 points

    Hi Alireza,

    The SCLK is the serial interface SPI clock, not the ADC clock, which is labeled as CLKINP/CLKINM in the schematics. There is no additional wires connecting from these clock nets to the FMC connector at all, as a result, this is not possible without designing an additional interposer/breakout board to go between the FPGA board and the FMC-ADC adapter board, whose purpose is to break out the FPGA clock. Clocking high speed data converters using an FPGA is not recommended as the jitter of the FPGA clock output will significantly degrade the performance of the data converter, well below datasheet specifications. In this instance, I would suggest to use a clock synthesizer and share a common reference oscillator between the FPGA and the clock synthesizer. In this case, I would suggest LMX2572LP in your final system design as it is very affordable and high-performance device. Is there an option to break out any reference oscillator between 5MHz and 125MHz? Do you have schematics that you can share from the Zynq 7000? If so, I can try to sample you an LMX2572LP EVM for your evaluation. 

    Thanks, Chase 

  • 0 in reply to Chase W
    Prodigy 10 points

    Hello Chase,

    Thank you for informing me on the difference between the SCLK and CLKINP/CLKINM. As I understand, the breakout board would have to connect to the Zedboard with a FMC connection and then to the FMC-ADC-Adpater with another FMC connection while containing the LMX2572LP, clock synthesizer, to send the clock signal from the FPGA to the ADC. Is this a correct understanding?

    The schematic of the Zedboard with the FPGA can be found in this link here:
    https://www.avnet.com/wps/wcm/connect/onesite/1661cca0-66e9-40c0-94fa-a85ade184a77/ZedBoard_RevD.2_Schematic_130516.pdf?MOD=AJPERES&CACHEID=ROOTWORKSPACE.Z18_NA5A1I41L0ICD0ABNDMDDG0000-1661cca0-66e9-40c0-94fa-a85ade184a77-nxyWZ3l

    In this next link, you can find the on-board oscillation values on page 19 of the PDF under "2.5 CLock sources" stating 33.3MHz for PS and 100MHz for PL:
    https://www.avnet.com/wps/wcm/connect/onesite/922900e3-3d57-4cc7-883f-a8b9fbea0cd0/ZedBoard_HW_UG_v2_2.pdf?MOD=AJPERES&CACHEID=ROOTWORKSPACE.Z18_NA5A1I41L0ICD0ABNDMDDG0000-922900e3-3d57-4cc7-883f-a8b9fbea0cd0-nxyWMFS

    I am wondering, rather then a breakout board, could I potentially build a board connecting to the Pmod of the Zedboard. The board would contain the clock synthesizer and send the clock output into a SMA port, connecting to the ADC via SMA cable. Four of the five Pmods are connecting to PL, so I believe they should be capable of outputing a 100Mhz signal from the FPGA to the clock synthesizer. This can be seen in the same PDF above on page 23 under "2.9.2 Digilent PmodTm Compatible Headers (2x6)."

    Thank you,
    Alireza

  • 0 in reply to Alireza Ranjbar
    TI__Mastermind 22060 points

    Hi Alireza,

    On second look, connecting the reference between the ADC clock and the FPGA reference oscillator is not necessary, my mistake.

    My previously suggested breakout board approach would allow for you to externally break out and connect a clock generated by the FPGA (yielding poor ADC performance) to the ADC clock input using an external SMA cable. This is similar to your pmod thought in a way, however, in either case, you are not required to integrate the LMX2572LP into the breakout board for evaluation purposes.

    For now, you can simply use the LMX2572LP EVM to clock the ADC for evaluation. I've since checked and unfortunately, I am unable to sample this EVM, so my apologies in that regard.

    If you are planning to use the zedboard in your final system, you may consider designing a board which contains the LMX2572LP and use the VCC3V3 available at the pmod (first verify that the zedboard can supply 3.3V at 70mA (the LMX2572LP max current)). It's not recommended for customers to integrate development boards into final systems/products, however for one-off projects and or evaluation setups, there should be nothing wrong with that since the entire purpose here is to evaluate the hardware in your system as best as possible.

    Regards, Chase