Other Parts Discussed in Thread: TSW14J57EVM
Hello,
Question 1:
Are there any FPGA program routines and constraint files for the demo board of ADC09QJ1300EVM?
Question 2:
The ADC chips of ADC09xJ800-Q1 and ADC09xJ1300 series used by TI in Lidar scenario belong to over-sampling or under-sampling sampling in practical applications?
Question 3:
As shown in the following figure: One of the advantages of using ADC: Why can the 1GSPS sampling rate have the equivalent sampling rate of 25.6GSPS for 5n waveform? What is the principle?

Question 4:
The following figure shows the second advantage of using ADC: How is multiple capture averaging implemented? Does ADC complete multiple capture averaging and output waveform in one sampling period? Still need multiple capture averaging for multiple sampling cycles?

Question 5:
For typical Lidar applications, using ADC09xJ800-Q1 and ADC09xJ1300 series ADC chips, how should the cut-off frequency fc of the front-end anti-alias filter be selected?
For example, for ADC09xJ1300, for 5ns echo signal with 1ns rising edge in the specification, the cutoff frequency of anti-alias filter is fc<0.5 * 1.3GHz?
Thanks!
