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ADS5474 Maximum Clock Jitter

Tuan To
Prodigy 210 points
Other Parts Discussed in Thread: ADS5474

Table 2 - Recommended RMS Clock Jitter on ADS5474 Datasheet states that the maximum clock jitter for input frequency of 350MHz is 144 fsec RMS. Is this 144-fs RMS jitter based on a certain offset frequency range? What is the offset frequency range that 144-fs RMS jitter is derived from? For instance, the datasheet of the VS-702 ( a Vectron International oscillator) indicates that the oscillator has a typical jitter of 0.1 ps-rms across 12KHz to 20MHz Bandwidth at carrier frequency of 622.08MHz.

  • 0
    TI__Mastermind 29220 points

    That jitter number is for all jitter out to the input bandwidth of the sample clock input buffer. 

    Equation 1 on that page states the relationship of SNR to the jitter on the sample clock, regardless of the data converter in question.  The clock path of the data converter will have some jitter of its own, called aperture jitter.  Equation 2 shows the relationship of the aperture jitter and the external jitter on the clock to that total jitter, which for gaussian distributions of jitter is square root of sum of squares.  Given the aperture jitter of the ADS5474, the external jitter requirements can be determined for a desired SNR, and you can't get better SNR than the aperture jitter allows even with a perfect external clock. 

    That the frequency components of the jitter in question are all frequency components out from 0Hz offset out to about the bandwidth of the clock circuit, which is probably around 2GHz or so.

    So if your oscillator vendor gives you a phase plot, then to get to the needed rms jitter number you would need to integrate that phase noise plot out to either the input circut bandwidth or if you put a bandpass filter on the clock then out to the bandwidth of the bandpass filter.

    Regards,

    Richard P.