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ADS1256: Time for a data read cycle

David Huang
Intellectual 2285 points

Part Number: ADS1256

Hi PADC team

What would be the time required for a single data read cycle when input frequency is 7.88MHz?

A single data read cycle stands for:

DAC data ready(DRDY Lo) → WAKEUP signal from SPI and send RDATA command → read the conversion data → DAC data ready(DRDY Lo)

Regards

  • 0
    TI__Guru 59541 points

    Hi David Huang,

    The answer to this question is included in the ADC datasheet - have you reviewed this document yet, specifically pages 20-22? Is there something in particular that is not clear?

    Note that the data rates, etc., will scale with the clock frequency, since the datasheet uses the nominal clock frequency of 7.68 MHz. Therefore, if you are using a 7.88 MHz clock, the data rate would scale by a factor of 7.88 / 7.68 = 1.026.

    Let me know if you have any additional questions

    -Bryan

  • 0 in reply to Bryan Lizon86
    TI__Intellectual 2285 points

    Hi Bryan

    Thanks! Missed the part...

    Another question:

    My customer reported that they used ADS1256EVM and the board worked just fine.

    However, after removing ADS1256 from the board and performed several test on device under AVDD = 5.0V, DVDD = 3.0V, the device failed to read data(DRDY stayed High)

    They think they got the setting wrong, could you please help check their questions as below?

    1. Is it fine to send the data as Address(1 byte) + Register value(1 byte)? Communication was at 100k-3MHz frequency

    2. STANDBY→WAKEUP→RDATA→WREG was sent after the power on but the device did not respond, is there any additional settings required for initializing the device to get one-shot mode data?

    Regards

  • 0 in reply to David Huang
    TI__Guru 59541 points

    Hi David Huang,

    Note that the SCLK period is relative to either fCLK (min) or fDATA (max). Therefore, if you are using a 7.88 MHz fCLK, the fastest SCLK frequency you can use is fCLK / 4 = 7.88 / 4 = 1.97 MHz. Therefore, you cannot use a frequency of 3 MHz. I have copied this information from the datasheet, as shown below.

    Does the ADC toggle the DRDY at any time, or under any circumstances? Have you seen any activity on DOUT? If you are not seeing anything on DRDY or DOUT, this might mean the ADC is not powered properly, or the CLK signal is not being applied correctly.

    A very easy test to perform is to power the ADC, apply the CLK signal, then take the SYNC pin high. At this point you should see DRDY toggling at approximately the default data rate (30 kSPS). Note that you do not need SCLK or any commands to make this work. If you do not see DRDY toggling under these conditions, then you have a power supply or CLK issue.

    -Bryan