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DAC38RF84: PLL Locked but CLKTX_P/N no output

Amy Luo
Expert 6895 points
Part Number: DAC38RF84


Hi team,

One of our customer's issues, I'm forwarding it below, could you please provide some troubleshooting suggestions?

I do not have an EVM board and I am debugging the DAC38RF84 with a homemade board and have a strange problem. I want to test the frequency of the FDAC via the CLKTX_P pin and when I do not use the on-chip PLL, I can measure the correct frequency at CLKTX_P. But when I used on-chip PLL, I found that CLKTX_P had no frequency output, only a 750mV DC voltage, read 0x05 register bit0 is 0,Indicates that the clock is locked. I have configured the page 4 register address 0x0b  data 0x0000;address 0x0c  data 0x2f00 ; do I need any other settings? Here is a list of my register configurations, I use CLK_P/N as the clock input at 180MHz. LMFSHD = 82121, 16x Interpolation. K=32.The sampling frequency is 5760MHz. 

000001
007863
011880
0200FF
0300FF
040000
050000
090004
0AFFFF
0B0000
0C2F00
0DF000
1B0100
230000
241000
310400
320708
33330C
340000
350018
3B0000
3C82A1
3D0088
3E0969
3F0000
090001
0A88BF
0C26E2
0D8301
0E00FF
0F1F83
10FFFF
11FFFF
170000
190000
1C0000
1D0000
1E0000
1F0000
202000
210000
220000
230000
240030
25B700
278888
280000
290000
2A0000
2B0000
2C0000
2D1FFF
2E1FFF
2F0001
302000
328800
330800
460044
47190A
4831C3
4AFF03
4B1300
4C1F07
4D0101
4E0F4F
4F1C60
500000
5100FF
5200FF
530700
549FE1
5C0001
5E0000
5F3210
607654
640000
650000
660000
670000
680000
690000
6A0000
6B0000
6C0000
6D0000
6E0000
090002
0A88B0
0C2402
0D8300
0E00FF
0F1F83
10FFFF
11FFFF
170000
190000
1C0000
1D0000
1E0000
1F0000
200000
210000
220000
230000
240020
25B700
271144
280000
290000
2A0000
2B0000
2C0000
2D1FFF
2E1FFF
2F0000
300000
320800
330800
460044
47190A
4831C3
4A0003
4B1300
4C1307
4D0101
4E0F4F
4F1CC1
500000
5100FF
5200FF
530100
548E60
5C0003
5E0000
5F3210
605764
640000
650000
660000
670000
680000
690000
6A0000
6B0000
6C0000
6D0000
6E0000
090001
240000
090002
240000
090001
5C0000
090002
5C0000
090004
0AFFFF
090004
090004
090004
0A7FFF
090000
007863
090001
090001
090001
240020
090002
090002
090002
240020
090001
090001
090001
5C0003
090002
090002
090002
5C0003
090000
090000
007860
040000
050000
090001
640000
650000
660000
670000
680000
690000
6A0000
6B0000
6C0000
6D0000
090002
640000
650000
660000
670000
680000
690000
6A0000
6B0000
6C0000
6D0000
090000
090000

Best Regards,

Amy Luo

  • 0
    TI__Guru* 91947 points

    Amy,

    Did you tune the PLL? If not, it will not be locked. Try using the values from the attached file. This has the PLL locked with a VCO tune value of 49 using all of your settings.

    Regards,

    Jim

    8212_Fs_5760_PLl_16x.cfg

  • 0 in reply to jim s
    TI__Expert 6895 points

    Hi Jim,

    Thank you for your support.

    Here's what I've received from the customer:

    I adjusted the PLL and the clock was locked. There is no analog signal output according to the register configuration you provide, and configuration of the registers is difficult without an EVM board. Could you please provide the register configuration for nco_only mode so that I can test and find the problem.My requirement: CLK_P/N is used as the clock input at 180MHz.LMFSHD = 82121, 16x Interpolation.K=32.The sampling frequency is 5760MHz, only NCO1 is used, the frequency of NCO1 is configured as 200MHZ, 1 pair of IQ inputs.

    Please also provide the register configuration in normal mode, my SYNC signal is already high, the SYSREFClk frequency is 1.40625 MHz and the NCO frequency is 1.26G.

    Also, after I get the register configuration , do I need to write it sequentially to work properly, or do I need some sort of sequence or steps to work?

    Any comments and explanations would be much appreciated.

    Thanks,

    Amy

  • 0 in reply to jim s
    TI__Expert 6895 points

    Hi Jim,

    Below is the follow-up question for this customer, could you please give your comments.

    Today I wanted to test whether the PLL is locked by the Alarm pin and found that the Alarm pin output is 0 regardless of whether the PLL is locked or not. I have configured the registers as: Page0, address0x00, data 0x7803; page4 address0x1B, data 0x0000; when the clock is not locked, Register 0x05, bit=1, status is correct, but the Alarm PIN test is 0.Does this indicate that the chip is broken?

    Best Regards,

    Amy

  • 0 in reply to Amy Luo
    TI__Guru* 91947 points

    Address 0x1B in page 4 needs to have data value of 0x100 to set the alarm pin to PLL/80. Register 0x05 bit 0 has to be cleared by writing 0x0 to it before reading it. Bit 0 should be 0 with the PLL locked. 

    Attached are the register settings for your setup mentioned above.

    821_5760_DAC_PLL_180_ref_1260M_NCO.cfg