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TI-JESD204-IP: JESD204B configuration between FPGA and DAC37J82

Brooke
Prodigy 120 points
Part Number: TI-JESD204-IP
Other Parts Discussed in Thread: DAC37J82EVM, DAC37J82,

Hi TI team,

I got two EVMs on the hand TSW14J56+DAC37J82. According to the DAC37J82EVM user guide, I can make the quick-start prodedure succesfully.

We use LMF=222 configuration for the DAC37J82.

In the next step, we want to make a copy of this JESD204B project in our own prototype. We are using ZYNC7000 FPGA  now.

Could you please let me know your JESD204B configurations based on this quick-start prodedure? Both on FPGA and DAC side are appreciate.

And we still need TI JESD204B IP in our design.

Best Regards,

Brooke

  • 0
    Prodigy 120 points

    Another points below:

    With the example configurations above, I found the FPGA GTX reference clock is 153.6MHz (GTX_CLK_P/N). It's the half of the DAC sampling rate (307.2M).. 

    This 153.6MHz clock is used for JESD204B reference CLK. Did you do the double of this CLK and then use it in the GTX? Or would you please share with your clock tree in the FPGA with this 153.6M input clk? With many thanks.

  • 0 in reply to Brooke
    TI__Mastermind 18081 points

    Hi Brooke,

    The JESD parameters for the mode that you are requesting, DAC3XJ82_LMF_222, are shown below and shown in the Quick Start page of the GUI. 

    LMFS = 2221 (See the DAC datasheet for additional information)

    K=10

    Data Rate = 368.64MHz 

    Serdes Rate = 7.3728Gbps

    For this mode the DAC37J82EVM is using the LMK in PLL mode and the VCO that is being used is 2949.12MHz. This is then divided down in the LMK to provide the DAC reference clock and the FPGA clocks. 

    The LMK output configurations can be viewed in the DAC GUI under the LMK tab.

    Access to the TI-JESD204-IP can be requested using the following link: https://www.ti.com/tool/TI-JESD204-IP 

    Regards,

    David Chaparro