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ADC12D1620QML-SP: AutoSync

Part Number: ADC12D1620QML-SP


Once the AutoSynce is configured correctly by monitoring DCLKs from all ADC via an FPGA or oscilloscope, the same register settings can be used every power cycle?
Or every power cycle, users have to again find out correct register setting to get aligned DCLKs by monitoring an FPGA or oscilloscope?

Best regards,


  • Hi,

    Once AutoSYNC is configured correctly and verified on all the ADC's the same register settings should wok from power cycle to power cycle given the sampling clock is getting to the each ADC with same relationship as before.