ADC12QJ800-Q1: How to splice the data received by the FPGA receiving end and sent by AD?

Katherine Wang

Part Number: ADC12QJ800-Q1
Other Parts Discussed in Thread: ADC12QJ800

Hi Team,

I'm using the ADC12QJ800 chip's JMODE0 mode to collect data. Could you tell me how to splice the data received by the FPGA receiving end to obtain the sampling data?

Kind regards,

Katherine

over 2 years ago

0 Katherine Wang over 2 years ago

TI__Intellectual 2210 points

Katherine Wang said:
Could you tell me how to splice the data received by the FPGA receiving end to obtain the sampling data?

According to the JMODE0 mode, I'll use the corresponding relation between the data received by the ADC FPGA receiver JESD IP and the 12bit data sent by the ADC.

0 Neeraj Gill over 2 years ago in reply to Katherine Wang

TI__Mastermind 20541 points

Hi Katherine,

Here is the tranport layer table from the datasheet which can be used to see how data to the FPGA in JMODE0.

Regards,

Neeraj

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ADC12QJ800-Q1: How to splice the data received by the FPGA receiving end and sent by AD?