DAC7802: Charge injection seems to 10 times (or more) larger in my implementation

Hi Mike,

For my reference, could you share a sketch of your schematic? How are you measuring this glitch energy? With just an oscilloscope? Are your probes compensated?  Can you share a scopeshot of the glitch?

Hi Paul,

Here is a link to a folder with an schematic clip and oscillogram:

https://drive.google.com/drive/folders/1D48yqeanTNqpD8h8npPOCBu2si96SIxV?usp=sharing

The schematic image shows two identical channels fed with the same DAC7802.

U18 was probed at its output (pin 1) for the capture.

The dac is being fed with a slowly incrementing count which includes the full range of the DAC.

C86 was 20pF for this capture; increased from 10pF to reduce the pulse area (volt*seconds; not energy). The power supply pins for the DAC and U18 do not show this noise pulse, nor does the V_REF_A pin. Increasing C86 further reduces bandwidth too much (we want fairly flat response to 500kHz).

I also added a 100 OHm resistor to ground at the output of U18  for this capture to mimic the conditions specified in the datasheet. No change was seen.

The same noise appears at the BNC for VDAC2 when plugged directly into an oscilloscope, albeit lower and wider.

You can see the pulses occurring over regular intervals related to how many (and which) bits are changing.

I have also added a layout snippet to the folder showing the relationship between the dac and U18 (and the compensation capacitors between them).

Setup and hold look good for the noisy output periods.

Thank you for your help!

I am reviewing this now.

Hi Michael,

I wonder if we could be seeing a few different things here:

1. Scope compensation (a bit unlikely) - could the fast steps indicate your probes here? Can you make sure they are compensated for the input? Maybe a high-z active probe would be better?

2. op amp settling - you have a pretty fast amp here, so I don't necessarily this this is the strong candidate.  Does removing the compensation cap help at all?

3. Can you move the reference to GND? Like externally short the reference pin to GND and sweep the codes then.  Do you still see such high glitch?

Thanks,

Paul

Hi Paul,

As noted previously, the noise is seen at the BNC connector, wired directly to the oscilloscope (no probe). I did check my probe and tuned in a bit, but the compensation signal was less than 5% off. Rechecking the DAC output with the compensation reset gave 65mVpeak injection pulse amplitude with the same full scale ramp and Vref set to about 80mV (to reduce dependency on the test signal while still providing it as a reference for location within the code sequence).

I have used a 10MHz opamp with similar results.

I have used different compensation caps. Reducing this value (to 5pF, for example) makes the pulse larger. Increasing it beyond 20pF rolls off my signal beyond my tolerance (about -1dB at 500kHz). 

I see no impulse noise during these times at the VREF pin for this channel, so I didn't try grounding it (or bypassing it with a cap). I will try that next.

This is my loudest impulse noise DAC ever. Does this part number have a reputation for this kind of noise?

Thank you for your help!

I have added more images to the folder

https://drive.google.com/drive/folders/1D48yqeanTNqpD8h8npPOCBu2si96SIxV?usp=sharing

17301-5 U29p3_U29p4_nonzeroVref.jpg shows pin 3 of the dac (Rfb in, in yellow) vs. pin 4 of the dac (Vref in, in green) with the previous small VREF voltage. Note the lack of VREF noise corresponding with the VDAC_2_iFB.

I then set the VREF signal to 0V and bypassed it to ground with a 1uF capacitor from pin 4 of the dac to pin 1 of the dac. This modification is shown in 

U29_Vref_1uF_bypass.jpg

The resulting pin 3 of the dac (Rfb in, in yellow) vs. pin 4 of the dac (Vref in, in green) image is captured here:

U29p3_U29p4_1uF_VREF_to_gnd.jpg

While this reduces high frequency noise (which was being filtered out by subsequent stages previously), there is no effect on the 300nsec HAD op amp output signal feeding pin 3 of the dac.

I think I'll play with a capacitor from VREF_A to IOUT_A with a symmetric cap from IOUT_A to R_FB_A (C86).

Thank you for your help!

Michael,

Paul is out of the office for a couple of days, so it may take until Wednesday for him to come up with a replay. If I have a chance, I'll take a quick look at this one.

For future reference, it's best to append the images to the post. At work, we're locked out of google drive for security reasons.

Joseph Wu

Hi Joseph,

I tried uploading pictures, but this site won't let me. I resorted to Google drive because that's all I can do.

This picture was attached directly from my phone. i'll try that with the others.

Thank you for your help,

Mike Henderson

This is U29p3_U29p4_1uF_VREF_to_gnd.jpg referred to in a previous comment.

Tried various caps (100 to 400pF) from dac pin 2 (Iout_A) to gnd (dac pin 1) or to VREFin (dac pin 4), then flattened response with Cfb (C86 in schematic).

No 'flattened' results had smaller charge injection pulses than present topology.

Hi Michael,

Thanks for reattaching the images. Like Joe mentioned, Paul is out of office. He'll be able to review later this week, 

Best,

Katlynne Jones 

Are we seeing excessive digital feed-through here? I see that in you I_SUPPLY curve there is visible switching, is that digital feed-through there?

Which digital edge are you using to trigger the final update? Would it be possible to isolate that edge and add come RC filter to slow it down?

This device should not be producing this much glitch and architecturally it does not make sense.  It is also not known for being high glitch.

Hi Paul,

As described above, this image:

U29p3_U29p4_1uF_VREF_to_gnd.jpg 

Quoting from my comment above:

I then set the VREF signal to 0V and bypassed it to ground with a 1uF capacitor from pin 4 of the dac to pin 1 of the dac. This modification is shown in 

U29_Vref_1uF_bypass.jpg

The resulting pin 3 of the dac (Rfb in, in yellow) vs. pin 4 of the dac (Vref in, in green) image is captured here:

End Quote.

Since the Vref (green) waveform is much smaller than the charge injection pulse in the Rfb (yellow) waveform (and toggles at a clearly different rate), we can see that the charge injection pulse is not crosstalk from an external bit line. As noted earlier, the data are multiplexed between two channels, so no bit of the external bus says on long enough to result in the 500nsec long pulse we see in the Rfb waveform. This indicates that the pulse is induced after the internal registering of the bits for this channel. Since I don't see a pulse like this on any other pin of the IC (including the power and ground pins), I can't see how to address this with filtering of static pins on the dac.

The charge injection pulse trigger can be identified from 

U29p3_U29p4_1uF_VREF_to_gnd.jpg 

as channel 1 (Rfb), falling edge, 52mV. This level was adjusted to trigger on the largest charge injection pulse of the output (at Rfb). The un-magnified view in the same oscillogram shows this pulse relative to other charge injection pulses in the same ramp waveform.

If I look only at the first, narrowest part of the charge injection pulse (about the first 50nsec), I see what usually is identified as a charge injection pulse (by time scale). It is only the later part of this pulse, extending past 500nsec before falling below 50% peak amplitude, that is unusual and difficult (because of its low frequency content). I don't see noise on the AGND pin of the dac, but we don't really expect that, given the planar ground connections and proximity to ground connections of the following op amp. Layout reattached:

The external data bus edges occur more frequently and sooner than the charge injection pulse, so the external bus edges are not coupling onto the current outputs pins (they happen at different times).

Thank you for your help!

Hi Michael,

Sorry for the delay, I have been traveling.  So given the information you have collected, I am running out of ideas.  But here are a few other things to try or consider:

1. Can you short L3 on your board? Some of these current changes can be pretty fast and I have seen these beads cause trouble before.

2. Are you seeing this on just one DAC or just one pcb? can you try replacing the DAC or testing on another device? the peak glitches seem to be associated with bit 9, so maybe this device is damaged? If you do not have any spares, I can sample you a few.  feel free to email your address information to Frost@ti.com.

Thanks,

Paul

Hi Paul,

Since Vin is much quieter than the output (and has no noise corresponding in time to the output charge injection pulses), I'm not hopeful about further power input experiments. Adding the 1uF cap to the original 0.1 & 10uF caps made no difference.

The behavior is repeated across multiple boards; each with its own DAC.

Thank you for your help!

MIke Henderson

Okay, I will review this with my colleague who may have even designed this part to see if he has any other idea.  One other thing that sounds silly, but has bitten me many times - you scope shots show your probe as 10:1 - is it actually an attenuated probe?

Hi Paul,

Yes, as the notes here indicate, I probe internal nodes with compensation-checked 10:1 passive probes and monitor my system output BNC's with coax connections to other scope channels.

I have ordered a couple more opamp part numbers to ensure that this isn't some funky undocumented internal slew rate limiting issue that happens to correspond between an LT opamp and a JRC opamp.

Thank you for your help!

Mike Henderson

Hi Mike,

Paul has been traveling so his next response may be delayed. Please share the results of the new op amps when you get them. 

Best,

Katlynne Jones

Hi Katlynne,

Here are today's lab notes on other opamps for the I to V conversion:

3/29/23 11:32 AM
Other dual opamps to try for U18 on SN: 2001-5
MC33078D

With 10pF C86, largest pulse area is about 24nVsec and it rings for about 1.5 cycles with constant low level oscillation at 1.6MHz and 250nsec HAD.

Change C86 to 20pF. Area is now about 22nVsec with no oscillation and 280nsec HAD .

Try other opamp (NCV33272A).
Set C86 to 20pF. Area is now about 22nVsec with no oscillation and 260nsec HAD .

End Quote.

So with four different opamps including the two already tried, we still see about 20 times the nominal voltage-time area as that specified in the datasheet for the DAC.

Please share any other ideas that come to mind.

Thank you for your help!

Here is an image of the schematic segment which includes the noisy DAC circuit.

I will order the EVM and see if we have similar behavior.  This glitch seems far to large to be possible with this architecture, but you have ruled out a lot of other options, so I will check it.

Also, were these units order from a TI distributor?

Hi Paul,

The boards were assembled in Asia, with them acquiring the parts, so I can't be sure where they came from. I will send a picture of one of the packages for valid marking identification.

Most of the recent experiments were performed with this board & DAC.

Does this look 'authentic'?

Thank you for your help!

Officially, I cannot comment if a specific part is authentic unless it is returned to TI via the distributor that sold it, but I will see if the lot trace code is valid.

In the mean time, shoot me an email at frost@ti.com and I will sample a few device to you just to confirm.  I will likely not be able to test this in the lab without ordering some PCBs, so it would be fastest to sample you a couple units.

This is a gratuitous posting to satisfy the TI E2E design support forums query I received via Email regarding issue resolution.

I understand that you (Paul Frost) have shipped me verified DAC samples for me to try in my boards to ensure that present production parts do or do no exhibit this behavior.

Thank you for your continued support, Paul!

No worries.  Just some automated forum stuff

Hi Paul,

Your DAC7802 samples arrived today. I put one on my usual test board and see over 20nV-sec of pulse area at the output of the I-to-V buffer (U18 pin 1). This is what I usually see; what appears to be 20 times the specification for this part from TI.

I didn't fine tune the feedback capacitor for the buffer, but I don't find that this helps with area (it just trades off pulse width for peak height).

Please let me know of any other recommendations.

Thank you for your help (and samples)!

hmm, okay.  Then we are likely in two spots now - the performance has changed over time and we need some characterization, or there is something really weird on your board

Ill shoot you an email offline and we will see the best way to move forward.  We can build some test hardware locally to confirm, but either way, your application will see some delays.  Maybe we can move you onto a different part in the meantime.