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ADS52J65: ADS52J65: Which JESD204B signals require length matching?

Peter Roos
Prodigy 100 points
Part Number: ADS52J65


I realize the question has been asked before but reading the various blogs and ADS52J65 datasheet, I just want to confirm that my understanding is correct regarding trace length matching in my particular setup, which matches the JESD204B example in the ADS52J65 datasheet, page 124, figure 158. 

I'm using two ADS52J65 JESD204B ADC's in my design, a Xilinx US+ FGPA where I use two GTH banks and a Clock Generator device in a subclass 1 setup in order to achieve deterministic latency using SYSREF as timing signal.

Question 1: Is my understanding correct that based on the system diagram below, trace length matching is required for:

---------------------------------------------------------------------------------------
- The ADC_SYSREF to DEV_CLK signals between the two ADC's.
- The FPGA_SYSREF to FPGA REFCLK1/2 signals BUT there is NO requirement to match FPGA to ADC signals.
- TX_TRIG for ADC1 and ADC2.
- SYNC for ADC1 and ADC2 BUT there is NO requirement to match TX_TRIG to SYNC signals. 
---------------------------------------------------------------------------------------


Question 2: ADS52J65 datasheet page 132 states the following for the CML outputs: 

- CML traces require a controlled impedance of 100 ohm differential. The routing of different lines must be matched as much as possible to minimize inter-lane skew. However trace length matching is less critical for the JESD interface as compared to LVDS interface.

Is there a practical limit on "as much as possible" when it comes to trace length matching for the CML outputs?


  • +1
    TI__Expert 4920 points

    Hi Peter, 

    Your understanding for Q1 is correct. Just a minor comment - length matching on the SYNC lines might not be required if you are using subclass1. But it is good practice to match the lines if you can afford it in your PCB layout. This might help in future debugs/work-arounds in case your SYSREF line is not working, then you can switch over to subclass 2. 

    JESD IP on your FPGA can handle CML lane skew. Maximum lane skew that it can handle would depend upon the elastic buffer size that is available in the FPGA. However, this comes at a cost in terms of increased latency. I found an article from the FPGA vendor here - https://www.intel.com/content/www/us/en/docs/programmable/723907/22-1-1-0-0/programmable-rbd-offset.html that might be helpful. 

    So, it depends on your layout and overall latency requirements. If your layout can afford good length matching (within +/- 50 mils) across CML lines then you can realize low latency JESD link. 

    Thanks,

    Karthik

  • 0 in reply to Karthik Nagabhushana
    Prodigy 100 points

    Thanks Karthik,

    This helped clarify our use case and I think I have all the information that I needed and I am glad to see my understanding was correct Slight smile

    Regards,

    Peter

  • 0 in reply to Karthik Nagabhushana
    Prodigy 100 points

    Hi Karthik,

    I have one additional question and I hope I can still ask that here in this thread:

    The ADS52J65 datasheet page 132 states the following in section 10.1 Layout Guidelines:
    --------------------------------------------------------------------------------------
    Some layout guidelines associated with the layout of the high speed interfaces are listed below:
    • The length of the positive and negative traces of a differential pair must be matched to within 2 mils of each
    other.
    • Each differential pair length must be matched within 10 mils of other differential pairs.
    --------------------------------------------------------------------------------------

    Is this guideline referring to the differential analog inputs, the differential CML outputs or the differential SYSREF_P/N and CLK_P/N signals, or for all them?


    Best, 

    Peter

  • 0 in reply to Peter Roos
    TI__Expert 7130 points

    Hi Peter,

    Corresponding to your question, please find my comments:

    1.  The length of the positive and negative traces of a differential pair must be matched to within 2 mils of each
    other.
    2.  Each differential pair length must be matched within 10 mils of other differential pairs.

    Analog Inputs: Low frequency signals (typically order of MHz) -> point 1 should be followed. Following point 2 is not necessary. 

    CML lanes: - Point 1 should be followed. Point 2 is not mandatory.

    SYSREF/SYNC/CLK - both point 1 and point 2 should be followed

    LVDS DOUT/DCLK/FCLK - both point 1 and point 2 should be followed 

    However, if the space and layout permits, there is no harm in following both 1 and 2  

    Thanks & regards,

    Abhishek