Hi,
I m using FPGA as the Master for acquiring the data from ADS8330 ADC. The control signals
serial clock(25Mhz), Convert start pulse are generated by FPGA.
The conversion clock for ADC is the Internal Osc clock of 21Mhz.
However while sampling the data on the falling edge of the SPI clock i always read the data out from ADC as Zero.
Is there anything i m missing as far as timing is concerned. Please help.
Hardware configuration:
1. CS, REF and COM pin are grounded
2. SDI is pulled up to 5V
3. +IN1 and +IN0 are shorted and applied to the same input voltage
4.conversion clock is internal oscillator clock.
5. CFR map is the default configuration.
Points considered for generating the control signals inside FPGA:
1. A low CONVST pulse of 50ns.
2. 40ns delay between falling edge of CONVST and rising edge of SCLK
3. SCLK frequency is 25Mhz
4. The minimum time between two consecutive CONVST signals is 21 CCLKs (conversion clocks)
Regards,
Priya
