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Problem in Data Acquisition of ADS8330

priya nebhwani
Prodigy 70 points
Other Parts Discussed in Thread: ADS8330

Hi,

I m using FPGA as the Master for acquiring the data from ADS8330 ADC. The control signals

serial clock(25Mhz), Convert start pulse are generated by FPGA.

The conversion clock for ADC is the Internal Osc clock of 21Mhz.

However while sampling the data on the falling edge of the SPI clock i always read the data out from ADC as Zero.

Is there anything i m missing as far as  timing is concerned. Please help.

Hardware configuration:

1. CS, REF and COM  pin are grounded

2. SDI is pulled up to 5V

3. +IN1 and +IN0 are shorted and applied to the same input voltage

4.conversion clock is internal oscillator clock.

5. CFR map is the default configuration.

Points considered for generating the control signals inside FPGA:

1.  A low CONVST  pulse of 50ns.

2. 40ns delay between falling edge of CONVST and rising edge of SCLK

3. SCLK frequency  is 25Mhz

4. The minimum time between two consecutive CONVST signals is 21 CCLKs (conversion clocks)

Regards,

Priya

  • 0
    TI__Guru**** 176271 points

    Hi Priya,

    Welcome to the forum!  Can you possibly post a screen shot showing the control signals (CONVST, SCLK, EOC/INT, etc) you send to/receive from the ADS8330?  By your description above, nothing sounds out of the ordinary.

  • 0 in reply to Tom Hendrick
    Prodigy 70 points

    Hi Tom,

    Will  be able to send you the snapshots captured on signaltap by tomorrow.

    Meantime can you please clarify one more doubt, which is whether the falling edge of FS/CS  (chipselect pin) is

    required to start  the cycle or it can be grounded as is in our case (CS is grounded in hardware)

     

    Regards,

    Priya

     

  • 0 in reply to priya nebhwani
    TI__Guru**** 176271 points

    Hi Priya,

    My apologies here - I missed the point above on your original post about the /CS line being grounded.  The FS/CS input must toggle, it can't be tied low.  The falling edge of FS/CS is the mechanism which starts the I/O cycle.  Toggling CONVST is the mechanism which determines the point at which the input switch to the sample and hold capacitor opens.