Other Parts Discussed in Thread: ADS42JB69EVM
I am able to correctly see at the output of my connected FPGA all of the ADC test patterns except for 2:
1. Deskew pattern - I am getting AAA8h, which I believe is correct given that on page 34 of the datasheet, it says "In ADS42JB49 two LSBs of 16-bit data are padded with 00." According to this post, the datasheet (which says it should be 3AAAh is wrong and) it should be 2AAAh, which would pad the 2 MSBs. All of the other data I am receiving also has the 2 LSB's padded.
2. 8 point sine - I am receiving A57C 8000 5A80 0000 5A80 7FFC A57C 0000 but according to the datasheet, I should be receiving 257C 8000 DA80 FFFC DA80 8000 257C 0000. To test what the correct output should be, I repeated the same configuration on a ADS42JB69EVM connected to a TSW14J50EVM-CB. Surprisingly, the output is the equivalent of a 14b 8 point sine representation (257C 8000 DA80 FFFC DA80 8000 257C 0000), though it is a 69EVM. What should I be getting when I set an ADS42JB49 to output the 8 point sine pattern? There are multiple inaccuracies that I have found in the datasheet so I wanted to check if the pattern I received could be expected.
Thank you.
