ADC3662: Differential Signal Level for CLKP and CLKM

Hi Ray,

Please refer to pg. 33 in the ADC366x datasheet (8.3.2 Clock Input / 8.3.2.1 Single Ended vs Differential Clock Input) for the differential clock input requirements. For differential clock input - "the clock input can be AC coupled externally. The ADC366x provides internal bias". Figure 8-14 shows the AC Performance vs Clock Amplitude. 

Pg. 8 of the datasheet shows VID / VCM, but they are listed above the 'Clock Input' parameters which could be why you had trouble finding them. I will check to see if this is a datasheet error. 

Regards, Amy

Hi Ray,

There is a datasheet sheet error here. The clock amplitude will directly impact the internal aperture jitter. The clock input has a small range threshold to trigger the sampling process. The smaller the clock amplitude, the longer the clock signal takes to go through that threshold - and this timing uncertainty equates to jitter in the time domain. The clock amplitude listed above specifies the device working properly. Please refer to Figure 8-14 for SNR vs. clock amplitude. 

Regards, Amy