ADC3422: adc3422 output data issue

Hello,

Can you clarify the issue you are seeing? It would also be helpful if you provided the test patterns you are seeing in HSDC Pro. 

Regards, Amy

I set test pattern all 0, but I see 100100100100......on wire1

what is HSDC pro

Hello,

Please provide the data that you are seeing to give us more information. What is your desired configuration? Are you using a custom design or a TI ADC3422EVM?

Regards, Amy

7418.schematic.pdf

It's my design, not TI demo. You can see my schematic attached.

The issue and configuraiton details of I relady provide to you at first message.

It's clear when set test pattern all 0 or all 1, the LVDS output doesn't go with expectation.

I am not sure what else you need.

Hello,

I setup our EVM in the lab and tested this for you with a ramp pattern test pattern. Please see the attached capture in the TI HSDC Pro software. I exported the register writes that I used to get the output capture.

Regards, AmyADC3422-RampChA.cfg

I am not sure what conclusion can be done from your result.

I already said in my first message, digtial ramp is same as expectation.

The issue I see is: 

1) Test pattern: all 0  (wire 1 jump between 1 and 0 )

2) Test pattern: all 1  (wire 1 jump between 1 and 0 )

3) Normal test: set fix anlaog input = 0V, the LVDS output value is jump back and forth.

Could you explain?

Hello,

I understand your configuration now, I will test these three conditions in the lab and let you know what I find.

Regards, Amy

Hello,

Here is the result I see on my end for an all 0 test pattern.

Additionally, this is the result for an all 1's test pattern: 

Does this match your result?

Seems match. It's 12 bit ADC, why Bit 11 is different?

Thanks, why I am testing this pattern is because I met an issue during normal test.

I connected a fixed 0V to ADC input and using offset binary form, then I expect the output should be 2048.

Actually I saw the the output is jump with about 40 count back and forth. 

The 1, 3, 5, 7, 9 ..........sample point read out ADC count is 2028

The 2, 4, 6, 8, 10.........sample point read out ADC count is 2068

Could you try it at your site?

The ADC3422EVM input is AC coupled, so the DC content is blocked. There is not a way for me to test this on our EVM.

So your test result is very stable, max 3 count change.

Do you have any ideas why my result jump back and forth as high as 40 count?

Hi Liping,

First measure the analog input pins common mode voltage. It should be around 0.95V. If its lower, then this is an issue.

Please disconnect all the amplifiers from the ADCs VCM connection per your schematic.

Only have one amplifier connected to the ADCs VCM pin. 

Then measure the common mode voltage on the analog inputs pins with only one amplifier connected.

Please verify and let us know.

Thanks,

Rob 

Hello Rob,

I measured the VCM pin at each amplifiers using oscillscope and multimeter.

It's 0.953V and looks quite stable.

So far, I did not disconnect all amplifiers.

Hi Liping,

Can you clarify what you are using as a sample clock source? TI recommends that you use a high quality source with low jitter to get the best-case ADC performance. From the schematic you posted, it appears that you are using a single-ended clock. However, please note that the datasheet recommends "for best performance the clock inputs must be driven differentially, thereby reducing susceptibility to common-mode noise" (pg. 43).

Regards, Amy

1. Please see below discussion. That's why I select this clock source.

https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1068911/adc3422-clock-selection-of-adc3422

2. YOu can see from attached datasheet. This clock has low jitter to meet the requirement.

ASTMLPA-18-50.000MHz-LJ-E-T.pdf

Hello Amy,

This is measurement of clock and calcuation of Jitter & SNR.

What's min requirement of SNR?

Also do you have any recommendation of oscillator part numbers?

637-1770980.pdf

should this part be better?

But it's 2.5V, I think it should not damage ADC since LVDS coupled by capacitor, right?

Hi Liping,

It would be better to clock the ADC differential, as the ADC expects. From the schematic above, the ADC is being clocked single-ended. So the input amplitude of the clock does not look as you have measured. It would roughly be half the amplitude.

We will try some things in the lab for you on our eval brd and get back to you early next week.

Regards,

Rob

Hi Liping,

Could you please test the DC voltage at CLKP and CLKM? The clock input's common mode voltage should be around 0.95 V according to the datasheet. 

Regards,
Ikram

test_wave.pdf

Hello Ikram,

Please see attachd measurement result. I don't see any issue.

But please check and give your comments. 

Hello Rob,

I am using resistor divider to measure external voltage ~100V to 100V.

Such kinds of code change is too big for me.

Do you have any solution recommend?

Hi Liping, 

These measurement look fine.

Regards,

Rob

Hi Liping,

I think we still need to verify the board/ADC is properly working.

If you can disconnect the entire frontend from the ADC and see how many codes are changing that would really help.

This will help isolate the issue. For example please remove R12 and R12 from the schematic you supplied to us. 

This will terminate the ADC. Now verify the code change on the output of the ADC.

Please update us when you can.

Thanks,

Rob

Hi Rob,

I removed R12 and R14, it goes much better. It's about 6 count peak to peak.
But I also did the same for another channel, I don't see the same improvement.
It still shows about 40 peak to peak.

Hi Liping,

Could you please tell us which channel you are observing this? Which resistors did you remove?

We would expect that if the amp configuration are same for each channel, it would have the same effect. Do you see this in all the other three channels?

- Ikram

5582.schematic.pdf

Please see attached schematic.

1) Channel D,  removed R12 and R14, obervation: 6 count peak to peak

2) Channel C, removed R53 and R55, observation: 40 count peak to peak

3) Channel B, not test

4) Channel A, keep resistor, observation: 16 count peak to peak

Hi Liping,

Thank you for getting back with the measurements. Could you please try disconnecting the amplifier power supplies (P5VA, M5VA) and see if the codes count peak to peak is lower for each channel? 

- Ikram

Hi Ikram,

After remove P5VA, M5VA,  test data:

1) Channel D, 3 count peak to peak (2042~2044)

2) Channel C, 3 count peak to peak (2022~2024)

3) Channel B, not test

4) Channel A, 2 count peak to peak (2038~2039)

But the avarage value of channel C and D is about 20 count.

Is there anything wrong with my current power design?

Or do you have any other power supply to recommend for my application?

Hi Rob,

You know, the ADC count 40 is about 20mV in my design.

20mV is too small for oscillscope to measure.

For normal oscilloscope probe, even you don't connect anything, there is some voltage wave jump and forth .

From previous test, it can tell root cause should be amplifier circuitry.

But how to improve? 

Hi Liping,

Just to be clear, now the codes count peak-to-peak is reduced. Before it was varying, probably due to amplifier noise, but now it's only ~2 codes. And another issue you are trying to address now if the offset (~20 codes) between channels (C and D) right?

A few questions:

- Are the digital LVDS outputs terminated with 100 ohms differential on the receiver side (FPGA?)?

- What bandwidth is needed for your application? From our calculation of the input RC network into the ADC is for around 3 GHz. If your application requires a smaller bandwidth, you could consider increasing the capacitor size for a lower cutoff. This could also reduce some noise

- if possible, could you share the full schematic, in particular the power supply circuitry? 

Regards, 
Ikram 

1) And another issue you are trying to address now if the offset (~20 codes) between channels (C and D) right?  [right]

2) Are the digital LVDS outputs terminated with 100 ohms differential on the receiver side (FPGA?)? [yes, please see below attached schematic]

3) What bandwidth is needed for your application? From our calculation of the input RC network into the ADC is for around 3 GHz. If your application requires a smaller bandwidth, you could consider increasing the capacitor size for a lower cutoff. This could also reduce some noise. [ Just need measure 50M, please suggest RC value]

4) if possible, could you share the full schematic, in particular the power supply circuitry? [see below attachment]1602.schematic.pdf