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ADS1281 SCLK Timing

CUIJVERS Yvan
Prodigy 60 points

Other Parts Discussed in Thread: ADS1281

Hello,

I'm designing an application around the ADS1281 and I improve difficulties to determine the best SCLK speed.
In the datasheet (page 6) the minimum SCLK period is : 2/fclk = 488.3ns with fclk = 4.096MHz. 
In the datasheet (page 25) : The data shift operation Read Data Continuous must be completed within four CLK periods before DRDY falls again or the data may be corrupted. So the 32-bits have to be shifted in 4/fclk = 976.6ns with fclk = 4.096MHz. That means one bit every 30.5ns ?? 32.768Mhz ??

What would be the speed of SCLK for these specifications :

CLK=4.096Mhz
Operation = High Precision Mode
SINC decimation = 8
FIR decimation = 32

Thanks a lot,

YCU

  • 0
    TI__Guru** 113765 points

    YCU,

    Welcome to the forums! 

    I think you have misinterpreted the statement on page 25.  If you were to look at the DRDY with a scope, you would see that if you do not read any of the data out the DRDY will pulse with the data rate.  So when DRDY goes low, it becomes the indicator that valid data is available.  When DRDY goes high, the new conversion result is being updated.  So, if you are in the process of reading out data, you must complete the entire read prior to 4 CLK periods before DRDY goes low again.

    Ultimately the best SCLK speed will be what fits into the min/max of the ADS1281 and your overall system.  In your case you can use any of the values within the min/max range shown on page 6.  This translates to 256kHz <= SLCK <= 2.048MHz.

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    Prodigy 60 points

    Thank you very much for replying so quickly. I agree with what you said. But I think it's very easy to misinterpret at first !

    You wrote : When DRDY goes high, the new conversion result is being updated.  So, if you are in the process of reading out data, you must complete the entire read prior to 4 CLK periods before DRDY goes low again.

    In the datasheet : DRDY is an output; when it transitions low, this transition indicates new conversion data are ready. DRDY resets high on the first falling edge of SCLK. When reading data in continuous mode, the data must be read within four CLK periods before DRDY goes low again or the data are overwritten with new conversion data

    So it means : when DRDY is low new data is ready to be shifted out; DRDY goes high after the first SCLK pulse; after it goes high I have to read 31 remaining bits in four CLK periods before new data are ready to be shifted out ?????

    It's what I understand by reading the datasheet. Recognize that it is easy to misunderstand...

    Yours sincerely,

    YCU

  • 0 in reply to CUIJVERS Yvan
    TI__Guru** 113765 points

    YCU,

    I realize that the wording can be confusing.  Usually we have better timing diagrams that show a complete cycle, or series of cycles and this would have shown the SLCK period and demonstrated the timing for the 4 CLK periods prior to the next DRDY going low.  Thanks for bringing this to our attention.  Hopefully we can make this clearer in the future.

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    Prodigy 60 points

    Hello,

    Thanks a lot. All the information you provided me where very useful to choose the right MCU for this project.

    Best Regards,

    YCU