ADC3644EVM: Latency Does Not Match the Data Sheet

Hi Jim,

Can you share the data and two methods you used to measure the latency?

Regards, Amy

Both a function generator and network analyzer were used to measure the latency into the ADC, through the FPGA and out a DAC.  I isolated the DAC in a separate test and am confident nearly all of the latency is due to the ADC.  The FPGA is only contributing 1 clock cycle (8 ns).  Channel 1 is the pulse from the function generator and channel 2 is the DAC output.  I was expecting something closer to 16 ns total.

Hi Jim,

Thanks for sharing the data you are seeing. If you can share a photo of your setup that may help us as well.

We would recommend using a good/fast oscope for this measurement, with a square wave analog input. Look at the input with one oscope probe and the digital output with another scope probe. 

I will set this up for you tomorrow in the lab and share with you the data I measure in the lab. 

Regards, Amy

Hi Jim,

I tried setting this up in the lab but realize that I will need to modify the board. I should be able to get you data in the next few days.

Regards, Amy

Any progress on the lab testing?

Hi Jim,

I apologize for the delay, I reached out to our validation team for feedback on how the device was characterized.

When sampling at 125M, you are correct you would expect to see a 8ns delay for one cycle latency. However propagation delay must also be considered - in the datasheet, this can be found on pg. 10 and is typ. 5ns with a 0.3ns clock lead (tcd). 

This means that the device will be 8ns + 5ns + 0.3ns = 13.3ns. 

For the FPGA, you are looking at one clock cycle - is deserialization done in one DCLK? How are you transferring this data - to the DAC on GPIO or another DDR interface (ie, could there be extra latency contributing here?)

The DAC cannot have zero latency. Can you provide the DAC part number?

Regards, Amy

> is deserialization done in one DCLK?

Yes

I've done some additional experimentation including measuring a pulse going into and out of the FMC board and the latency is still over 30 ns.  I did discover that the ADC3644EVM uses line drivers that add another 5.4 ns of latency on top of the ADC itself.

Were you able to modify the EVM board and confirm the 13.3ns result on the actual hardware?

Hi Jim,

I will relay the information to the validation team and get their thoughts. The board that was modified was damaged in the process, so we had to order another ADC3644EVM since we did not have another on hand in the lab. I will update you when the new one comes in.

Regards, Amy

I'm not surprised that the modifications were difficult.  Development boards should really be using physical jumpers instead of microscopic 0 ohm resistors.

Hi Jim,

Here are additional details from the validation team, using 50MSPS as an example (20 ns period): 

At 50 MSPS the bit period is 20ns. You see in timing diagram rising edge of DCLK starts the sample with 7LSB followed by 7 MSB:

Overlaying this with the measurements taken, you can see the latency from the sampled signal to the sample with MSB (high) is actually only ~30ns: 

In data sheet we give propagation delay of 5ns (typ) plus ~ 0.3ns clock lead plus one clock cycle digital latency which brings the total to ~ 25.3ns. This measurement is ~ 28ns, where probe capacitance likely accounts for the additional delay. 

Can you please provide your pulse data measurements? Can you also provide the DAC part number? We can also setup a call if you would like to further discuss. 

Regards, Amy

Additionally, we would appreciate if you could provide a block diagram or photos that help us understand your test setup. Can you also let us know where you are placing the probes to take the measurement?