ADS131M08: Reading samples completely asynchronously (ignoring DRDY)

Hi Jamie,

Yes, I've seen these types of questions about this a couple of times now. Funnily enough, I thought I had written something about it already but I can't seem to find the thread. Before I answer the questions directly, here's some old notes I have from our team:

Note, the device is not design to have a "conversion start" or "single shot" function. As soon as the device powers on, the device starts converting.

The device has an “output data buffer” and a “FIFO buffer”. Both buffers can only hold one conversion result.

The data output on the SPI is always from the FIFO buffer.

In the following examples I use the following notation to indicate which sample is in which buffer [# of sample in output data buffer | # of sample in FIFO buffer]

Example 1:

When the first conversion (#1) completes it is placed both in the output data buffer and the FIFO buffer [#1 | #1].

If you read the data right after the conversion completes, then you are reading result #1. The content of the buffers stays at [#1 | #1]. Means you can read out the #1 conversion result again if you would like to.

Now if conversion #2 completes it is again put into both the output data buffer and the FIFO buffer [#2 | #2].

If you read the results before conversion #3 completes, you read out result #2 and the buffers stay at [#2 | #2].

Example 2:

When the first conversion (#1) completes it is placed both in the output data buffer and the FIFO buffer [#1 | #1]

If the data from the FIFO buffer has not been read and conversion #2 completes, then the output data buffer holds the sample #2 while the FIFO buffer still holds sample #1 [#2 | #1].

If you read data now before conversion #3 completes, you will first read out result #1. The content of the buffers then changes to [#2 | #2].

If you read again you will read result #2 now. The buffers stay at [#2 | #2].

Now when conversion #3 completes it will overwrite the results in both buffers [#3 | #3].

Example 3:

When the first conversion (#1) completes it is placed both in the output data buffer and the FIFO buffer [#1 | #1]

If the data from the FIFO buffer has not been read and a new conversion (#2) completes, then the output data buffer holds the sample #2 while the FIFO still holds sample #1 [#2 | #1].

Now if conversion #3 completes and the FIFO has still not been read, then sample #3 overwrites both the sample in the output data buffer and the FIFO [#3 | #3].

In this case, both conversion result #1 and #2 are lost and cannot be read anymore.

Now, onto your questions:

Jamie Smith said:

My question is, what happens if an SPI read occurs at the exact time that a new sample is enqueued to the FIFO?  Is there potential for a race condition, where data is updated in the middle of the processor reading it?  Or does the FIFO have logic to keep a reading in the buffer during an SPI read? 

I want to confirm, but I believe the output data buffer would be updated as SPI is accessing the FIFO buffer but let me confirm with the team.

Best,

-Cole