Other Parts Discussed in Thread: DAC5682Z
Hi All,
I am trying to use DAC5682z EVM board with a Stratix II GX eval board using HSMC connectors to interface them. I am generating a simple saw-tooth pattern from the FPGA. The FPGA clock (DCLK half rate clock) and hence the data rate to the DAC board is set to 400 MHz. I am using a low frequency signal generator to provide the reference clock to the PLL in the DAC board to generate a (full rate) sampling clock at 800 MHz. I use the following code to generate the saw-tooth wave.
always @ (posedge DCLK)
DAC_Data_Reg <= DAC_Data_Reg + step_size;
Where DAC_Data_Reg and step_size are both 16 bit wide.
The problem:
The DAC works fine for small values of step_size (upto say 16'h0080). If I increase the step_size from (16'h0001) to say (16'h0200), the recovered output is highly distorted, the lower edge (starting point) of the saw-tooth is rounded up instead of being a sharp corner. Moreover, the transition from 0xFFFF to 0x0000 is not smooth even at small step sizes. The output shows distortion as the code changes from 0xFFFF to 0x0000.
Q1. I want to ask if there is some restriction on the maximum step change at the DAC digital inputs e.g. is there a limit that the output be changed less than (say) 10 mV per data update for proper operation?
Q2. Since changing the step_size also changes the frequency of the applied SAW tooth pattern so is there a limit on the frequency of the applied pattern?
Q2. Is there a setup and hold requirement for the DAC when using the DLL to adjust the data to clock skew? If yes, then please mention the specification in reply.
Regards,
Abdul Rehman Javed.
