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Config.5681 at various CLOCK Frequency

thu nguyen
Intellectual 510 points
Other Parts Discussed in Thread: DAC5682Z

hello Hamza,

1) I'll try your new code shortly.

2) Under DAC5682z EVM Control. There's box " Digital logic: enable/disable" . Which option should I use?

3) Could I set config.reg5681 as following for various clock frequencies. Please correct if settings are not correct.

thks,thu

(Attached this text for your modifications if needed)

DLL disable DLL enable DLL enable
Config# Deafult <125MHZ  125-150 175-200
0 1F 1F 5F 5F
1 10 10 10 10
2 C0 C0 C0 C0
3 70 70 70 70
4 0 0 0 0
5 0 0 O4 O4
6 0C 0C 0C 0C
7 FF FF FF FF
8 0 0 0 0
9 0 0 0 0
10 0 0 CD CF
11 0 0 0 0
12 0 0 0 0
13 0 0 0 0
14 0 0 0 0
15 0 0 0 0

 

  • 0
    TI__Expert 5820 points

    DCLK 125-150

    5F
    00
    C0
    70
    00
    00
    0C
    FF
    00
    00
    CD
    00
    00
    00
    00
    00

    DCLK 175-200

    5F
    00
    C0
    70
    00
    00
    0C
    FF
    00
    00
    CF
    00
    00
    00
    00
    00

    DCLK < 125

    1F
    00
    C0
    70
    00
    04
    0C
    FF
    00
    00
    C0
    00
    00
    00
    00
    00

     

    Regards,

  • 0 in reply to Hamza Fraz
    Intellectual 510 points

    Hi Hamza,

    1) The new Mat Lab code is working only with your config.reg5681 with CONFIG10=C0 (DCLK=1000mhz, fin=5mhz)

    2) I tried your new MAT Lab code for lower DCLK (50 and 100MHz) , the signal frequency is cut by half.

    3) When I load config file for DCLK =125-150 , the STATUS0 remains 0x1F instead of 0x5F ?

     

    thks,thu

  • 0 in reply to thu nguyen
    TI__Expert 5820 points

    1) Thu, are you changing the variable 'fs' to match your desired DAC clock frequency and regenerate the .mat file, each time you change your DAC CLK frequency?

    2) are you loading the .mat file I generated or generating new ones for 50/100 MHz. The one I generated was for DAC CLK = 1000 MHz.

    3) Lets clarify one thing here. DCLK = DACCLK/2; so when you say DCLK = 125-150, the clock going into the DAC should be 250-300. DCLK is the clock that TSW3100 generates for the DAC to transfer data into the DAC in a DDR fashion. DAC CLK is the clock that comes out of your signal generator and feeds the DAC EVM. The CONFIG10 values given in the data sheet are with respect to DCLK. Having these definitions cleared up, check your CONFIG10 settings.

  • 0 in reply to Hamza Fraz
    Intellectual 510 points

    hi Hamza,

    1)  We changed "fs" and "DAC clock" and generate new .mat file.

    2) I generate new .mat file for 50/100mhz  DAC clock .

    3) It's clear now that  DCLK = DACCLK/2. But I'm still not sure why, when the config.reg5685 file for DCLK = 125-150 is loaded,

      the STATUS0 is still remained  0x1F instead of 0x5F ?

     

    thks,thu

  • 0 in reply to thu nguyen
    Intellectual 510 points

    Hi Hamza,

    I set the correct DCLOCK for 125-150mhz, and issue with STATUS0 has been resolved. The STATUS0 has been changed from 0x1F to 0x5F.

    Thank you for your support.

    thu