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ADS8168: Queries regarding the serial interface of ADS8168

Jash Kothari
Prodigy 380 points
Part Number: ADS8168

Hi Team,

My customer is working on ADS8168 and they had few doubts regarding the serial interface of the same. Can you please help answer the below ?


1) We need to update DATA_CNTL register of the device. We are transferring the following pattern to ADC. There is a confusion regarding the same. Please confirm whether its correct
a) Transfer "0x0800AA" (Register Access)
b) Transfer "0x081001" (Output bits as ADC Conv Result + 4 bit Channel)
2) The device is configured as slave and a microcontroller as master. The controller is configured to acquire data in multiples of 8 bits. We want to operate the ADC in autosequence and repeat mode. But to ensure the integrity, we want to retrieve the channel ID along with data. The "DATA_OUT_FORMAT" field of "DATA_CNTL" register can be configured to get both channel ID and ADC data by assigning it as 01b. But in that case the bit count will be 16 + 4 = 20. The controller is configured to acquire data in multiples of 8. It will send either 16 or 24 clock cycles before CS is turned high. So how can we solve this issue ?

Thanks,

Jash 

  • 0
    TI__Mastermind 40610 points

    Hello Jash,

    Transfer 0x0800AA is correct to enable write to Interface and HW Config registers.  However, to append 4-bit channel ID, the correct Transfer is 0x081010.

    You can clock 24b for each SPI frame.  In this case, the first 16b is the conversion result, followed by the 4b channel ID.  The remaining 4-bits (LSBs) will be zeros.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    TI__Prodigy 380 points

    Hi Keith, Thanks for the reply. They have few other queries. Adding the same below.

     In ADS8168 datasheet, the CS high time width requirement is given as greater than 30ns and the conversion time, 'tconv' is given as more than 660ns.

     But in figure-1, the CS high time is almost equal to that of conversion time 'tconv' which should have a minimum value of 660ns.

     Please help clarify the following.

    1) So what is the actual requirement for CS high timing ?.

    2) Whether the CS width is having any relevance to the ADC performance other than satisfying the minimum width requirements ? or the CS rising edge

    3) To get maximum performance, can we issue SCLK for data transfer in the acquisition phase ? or should we wait for acquisition phase to be over ie Tconv + Tacq = 660 + 300 ns ? We require 6 channels of the ADC to be sampled at 100 KHz per channel.

    Thanks,

    Jash

  • 0 in reply to Jash Kothari
    TI__Mastermind 40610 points

    Hello Jash,

    1.  If /CS is held high for at least 30ns,  but less than 660ns, then you will read the previous conversion result.  The conversion is started on the rising edge of /CS, so you need to wait 660ns before taking /CS low to read back the latest conversion result.  So, in practice, you should follow the timing outlined in Figure 1.

    2.  If /CS is held high less than 30ns, then you may not get correct operation of the device, including proper start of conversion.  At a minimum, /CS needs to be high for 30ns, but in practice, it should be held high for the maximum conversion time, or 660ns for the ADS8168.

    3. You can clock data during the acquisition phase.  Since you need to operate at 600ksps (6 channels at 100ksps per channel), you can extend the acquisition time to 1000ns, which will relax the input amplifier requirements.  This is not necessary, but will allow more time for the external signal chain to settle.

    Regards,
    Keith