I want to know the digital value of Input Full Scale on the AD12DJ3200(JMODE16) xilinx FPGA Chipscope.
Please check if there is anything missing in ADC setting or getting digital value.
1. Device: AD12DJ3200
- JMODE 16 (Dual channel setting, but only B-Channel is used, Complex I, Q)
- FS_Range_A, FS_Range_B Register : 0x2000 (about 500mVpp)
- JESD204B connection -no Scramble - Data format: 2's Complement
- Disable Gain Boost
2. FPGA: xilinx xcku060
- Using JESD204 IP
- To check ADC Input Full Level through ChipScope (Digital value)
- Input Waveform : Sine Wave Adjust the ADC input level (RF input) to around 500mVpp based on the ADC Datasheet,
check the I and Q outputs of each 16bit in JMODE16 Since the LSB of 16bit is OVR_T, exclude it and add '0' (I[15:1] & '0', Q[15:1] & '0') to become Signed 16bit Value range of Signed 16bit is +32767 ~ -32768,
about +32000 ~ -32000 should be output when Full Scale Level is entered. However, in actual output, about half of the values are output.
Thank you!
Best Regards.