Other Parts Discussed in Thread: ADS1278
How can the ADS1278-SP be used in high speed (frame sync) TDM mode at 31.25 MHz if the DOUT1 timing is up to 31 ns?
The SP datasheet lists the SCLK and FSYNC to DOUT1 timing as taking up to 31 ns, tDOPD and tMSBPD respectively? At 31.25 MHz, the period is 32 ns, which would leave only 1 ns for round trip board and FPGA setup time. At the datasheet max of 32.768 MHz, the period is ~30.5 ns, which is less than 31 ns so the datasheet seems incompatible with itself. Or am I missing something?
We’re powering DVDD at 1.8V. The commercial ADS1278 shows the max tDOPD and tMSBPD is 25 ns. That’d leave 6 ns for board + FPGA timing, which is doable. Also, out application won't run the ads1278 over the full temperature range.
Thanks,
Chris
