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Original question:

AFE58JD48: Down-conversion

AFE58JD48: Data converters forum

Gabriel Wang1
Genius 4785 points
Part Number: AFE58JD48


Dear Expert

Question 1: The DC drift of each channel is relatively large. Is it the corresponding output offset of ±800 in the manual? Is this normal?


Question 2: Are there any suggested ways to optimize overload recovery time?

  • 0
    TI__Expert 7130 points

    Hi Gabriel,

    The output offset of the signal chain in terms of ADC codes for a 16 bit codes (0 to 65536) is +/- 800 codes.

    There are 2 modes of offset correction implemented in the device.

    1. LNA HPF1: Proprietary DC Offset Correction Feedback loop  - the LNA HPF1 can be disabled using the LNA_HPF_DIS register control, or by using the DIS_LNA_INTEG pin control. Disabling this HPF results in a large dc offset at the device output. Ensure that the LNA HPF1 is enabled

    2. Digital Offset correction: manual and auto offset correction. Please refer to section 10.3.7.1 Digital Offset in the datasheet.

    Regarding the Overload recovery: The device offers consistent and fast overload recovery with a 6-dB overloaded signal. For very large overload signals (> 6 dB of the linear input signal range), TI recommends back-to-back Schottky clamping diodes at the input to limit the amplitude of the input signal. 

    You can also use the PGA Clamp functionality to further optimize the overload response. You can refer to section 10.3.3.1 PGA Clamp for more details.

    Thanks & regards,
    Abhishek