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DAC 8168IC output Toggling

Other Parts Discussed in Thread: DAC8168

Hi,

 

  I am using DAC8168Ic ,this has been connected over a SPI interface to MPC5644 EVM board, The idea is to get a DAC output by sending the data over SPI, but the output vltage of DAC 8168 seems to be toggling, i have copied the code below can anyone give any suggesstion onit?

 

#include <math.h>
#include "MPC5644A.h"

extern void SpiDrvrInit();
extern void SpiDrvrWrite32(unsigned char cs,unsigned int databuff);

      
/* ****************************************************************************
 * PLL Code
 * ****************************************************************************
 */
typedef struct
{
    uint8_t    eprediv;
    uint8_t    emfd;
    uint8_t    erfd;
   
}T_FMPLL_INITVALS;

#define  FMPLL_200MHZ_INDEX  0
#define  FMPLL_130MHZ_INDEX  1
#define  FMPLL_256MHZ_INDEX  1

/*
 * Table containing initialisation values for FMPLL
 */
T_FMPLL_INITVALS fmpll_init_vals [] =
{
   
    {0x04, 0x32, 0x00},        // Fvco = 400Mhz Fsys = 200Mhz
    {0x03, 0x1A, 0x00},        // Fvco = 260Mhz, Fsys = 130Mhz
    {0x04, 0x40, 0x00},        // Fvco = 512Mhz, Fsys = 256Mhz
   
};
/*
 * Function to initialise system clock and PLL values
 *
 * In enhanced mode of operation, Fsys is calculated using the following equation:
 *           Fsys = fref * (EMFD / ((EPREDIV + 1) * 2 ^(ERFD + 1)))
 * In case of 564A EVK, the fref is 40Mhz.
 * (range from 256 to 512 Mhz)
 */
void initSysclk (int req_clk_index) {
  uint32_t esyncr1_val = 0xF0000000
                          | (((uint32_t)(fmpll_init_vals[req_clk_index].eprediv)) << 16)
                          | ((uint32_t)(fmpll_init_vals[req_clk_index].emfd));
  uint32_t esyncr2_val = ((uint32_t)(fmpll_init_vals[req_clk_index].erfd));
                        
  FMPLL.ESYNCR2.R = esyncr2_val;            /*Set */ 
  FMPLL.ESYNCR1.R  = esyncr1_val;       
  while (FMPLL.SYNSR.B.LOCK != 1) {};     /* Wait for FMPLL to LOCK  */
 
}

      
/* ****************************************************************************
 * SPI Code
 * ****************************************************************************
 */
static void initDSPI_B(void) {
    //configure pads
    SIU.PCR[105].R = 0x0600;    // Chip select DSPI_B_CS, AF1
    SIU.PCR[102].R = 0x0600;     // SPI Clock DSPI_B_CSK, primary
    SIU.PCR[103].R = 0x0500;     // DSPI_B_SIN, primary`
    SIU.PCR[104].R = 0x0600;     // DSPI_B_SOUT, primary
   
    // DAC GPIOS
    SIU.PCR[203].R = 0x0200;
    SIU.GPDO[203].B.PDO = 1;
    SIU.PCR[204].R = 0x0200;
    SIU.GPDO[204].B.PDO = 0;
   
    DSPI_B.CTAR[0].R = 0x7EAB000B;
    // configure controller
      DSPI_B.MCR.R = 0x90010001;     /* Configure DSPI_B as master with DSI Configuration*/
     
}


void SpiDrvrWrite32(unsigned char cs,         // chip select to be asserted
                    unsigned int databuff) // buffer containinng 16-bit data to be transmitted
{
    unsigned short *tbuffptr = (unsigned short *)&databuff;
    DSPI_B.MCR.B.HALT = 0x0;     /* Exit HALT mode: go from STOPPED to RUNNING state*/
    // Setting
   
    DSPI_B.DSICR.R   = 0x40080001;        // increase framesize to 32 bit and CS0 polarity & take from DSIASDR
    DSPI_B.DSICR1.R  = 0x00000000;
    DSPI_B.ASDR.R    = databuff;
    DSPI_B.MCR.B.HALT = 0x1;     /* Exit HALT mode: go from STOPPED to RUNNING state*/
   
}


   
/* ****************************************************************************
 * DAC Code - DAC8168
 * ****************************************************************************
 */
#define DAC8168_CMD_WRITE_REG            0x00
#define DAC8168_CMD_UPDATE_REG            0x01
#define DAC8168_CMD_WRTSELREG_UPDALL    0x02
#define DAC8168_CMD_WRTSELREG_UPDRESP    0x03
#define DAC8168_CMD_PWRDOWN                0x04
#define DAC8168_CMD_WRITE_TO_CC_REG        0x05
#define DAC8168_CMD_WRITE_TO_LDAC_REG    0x06
#define DAC8168_CMD_SOFTWARE_RESET        0x07


#define DAC8168_CHANNEL_ADDR_A            0x00
#define DAC8168_CHANNEL_ADDR_B            0x01
#define DAC8168_CHANNEL_ADDR_C            0x02
#define DAC8168_CHANNEL_ADDR_D            0x03
#define DAC8168_CHANNEL_ADDR_E            0x04
#define DAC8168_CHANNEL_ADDR_F            0x05
#define DAC8168_CHANNEL_ADDR_G            0x06
#define DAC8168_CHANNEL_ADDR_H            0x07
#define DAC8168_CHANNEL_ADDR_ALL        0x0F


void Dac8168Send(uint8_t cmd,uint8_t channel, uint16_t data)
{
    uint32_t spi_data = 0x00000000;
   
    // pull LDAC line up
    SIU.GPDO[204].B.PDO = 1;
    spi_data = ((uint32_t)(cmd & 0x0F)) << 24;
    spi_data |= ((uint32_t)(channel & 0x0F)) << 20;
    spi_data |= ((uint32_t)(data & 0x3FFF)) << 6;
    SpiDrvrWrite32(0x0, spi_data);
    SIU.GPDO[204].B.PDO = 0;
    return;
}



int main(void) {
    volatile unsigned short i = 0;
    int  adc_min = 0x0, ad_max = 0x1FFF;
    double deg , rad ;
   
    //initialise peripherals & pll
    initSysclk(FMPLL_256MHZ_INDEX);
    initDSPI_B();
       
   
    Dac8168Send(DAC8168_CMD_SOFTWARE_RESET, DAC8168_CHANNEL_ADDR_ALL, 0x0000);
    while (1){
        if (i < 0x3FFF)
            i++;
        else
            i= 0;
        Dac8168Send(DAC8168_CMD_WRTSELREG_UPDALL, DAC8168_CHANNEL_ADDR_H, 0x1FFF);
    }
}



  • Hi Anil,

    I will try and take a look at your code a little later today to see if something stands out. Generally, when I first power up and use this DAC, I try to write the broadcast mode command with the SW LDAC to write full scale to see if I am able to establish communication. I would consider writing 0x02FFFFF to see if I can set the device to full scale and have the output update. This command uses the software LDAC and bypasses the LDAC I/O pin. I would then take a look at the 3 SPI lines, /SYNC, SCLK, and DIN, to make sure it is writing what it should. Also, make sure that your /CLR pin is pulled high and, there is a reference voltage present (either internal or external).

    Regards,

    Tony Calabria

  • You will also want to take a look at your phasing and polarity of your SCLK and DIN line to make sure you have the data changing on the rising edge to be valid to be clocked into the DAC on the falling edge of SCLK.

    Regards,

    Tony Calabria