DAC3482

Hello Dounia,

- first : in the CDCE62005 VCO settings  the M&N settings: how do we choose the right input divider and feedback divider and prescaler.

I have attached some example CDCE62005 settings for you. The input to the CDCE62005 PLL is a 19.2MHz TCXO, and the output of the PLL are configured for 491.52MHz, 614.4MHz, and 983.04MHz. These are some of the common Telecom frequencies.

The M and N divider need to be set according to the PFD rating of the CDCE62005. The VCO needs to be tuned so the prescaler and the final output frequency matches. For more detail, please refer to the CDCE62005 datasheet.

- In input format tab: what's the difference between 2's complementary and binary format and wath is the advantage of using one and not the other?

For 2's complement, the digital code will range from -2^15 to +2^15-1. For offset binary, the code will range from 0 to 2^16-1.

The choice between the two format would depend on the digital output of the FPGA or ASIC. It is really a matter of system designer's preference, and there is no advantage of using one over another. 

- inverse Sinc filter is used to compensate the IQ amplitude?

 The inverse sinc filter is used to compensate the sinx/x response of the DAC output. The sinx/x response is inherent for all of the DACs due to zero order hold response. Please refer to the DAC3484 d/s for more detail.

-KH