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ADC12DJ5200RF: SYNC not asserted for JMODE3 and JMODE11

Saisri Bhairi
Prodigy 30 points
Part Number: ADC12DJ5200RF
Other Parts Discussed in Thread: LMK04832, LMX2594

Hi Team,

I am Saisri, I am using ADC12DJ5200RF in my design and it is interfaced with Kintex Ultrascale FPGA using JESD204B protocol.

1. The receiver is not asserting the sync signal when the ADC is configured with the JM3 with 9.6Gbps lane rate, 4.8GSPS sampling clock and four consecutive  K28.5 characters are received on each lane.

2. Sync from the receiver is not stable when ADC is configured with JM11 with 3.2GSPS sampling clock and also K28.5 characters are not received properly.

LMK04832 is being used for Rx Core clock and Sysref to both ADC and FPGA. 

Sampling clock is generated from LMX2594.

Please let me know if you need any other information.

Looking forward to hear from you.

Thanks.

  • 0
    TI__Mastermind 40480 points

    Hi Saisri,

    Please provide us the register write that you are also applying to the ADC during the bring up.

    If you can forward us a schematic with the clock circuits this will help too.

    Thanks,

    Rob

  • 0 in reply to Rob Reeder
    Prodigy 30 points

    Hi Rob,

    Thanks for your response. Below are the ADC register configuration for the JM3 mode.

    JM3
    x"0000B0",  ---reset adc x"0000B0",     
        x"800300",   -- High speed ADC - returns
        x"800400",   -- Chip ID register  - retu
        x"0030FF", ----1000mvp-p for CHA
        x"0031FF",
        x"0032FF", --1000mvp-p for CHB
        x"0033FF",   
        x"004801",   -- Enable pre-emphasis if jesd is not working
        x"006000",  --Dual channel with no decimation mode& CHA samples INA±, CHB samples INB±.
        x"020000",   -- Disable JESD  
        x"006100",   -- Stop calibration
        x"020103",   -- JMODE 3 is selected
        x"02021F",   -- Program KM1 (K-1) , K = 5, KM1 = 4 
        x"020403",   -- Scrambler enabled, Signed 2's complement data format, ~SYNCSE used as ~sync
        x"020504",   -- JTEST Test pattern control register (Ramp Test mode selection)
        x"020600",   -- DID = 0
        x"0211F2",   --over range threshold 0
        x"0212AB",   --over range threshold 1
        x"02130F",   -- Enables overrange status output pins
        x"00621A", --enables background offset calibration
        x"806A00", ---returns the calibration status
        x"006B00",--cal pin config
        x"006C01",--cal soft trigger
        x"006E49", ---low power background calibration
        x"007000", ---calibration data enable
        x"002930", ---manual sysref calibration
        x"002970",---manual sysref calibration
        --x"00297B",---manual sysref calibration
        x"006101",   --- Enable calibration
        x"020001",   --- Enable JESD
        x"820800", ---reading the status of the JESD link
        x"021602", --digital channel binding
        x"022000",   -- NCO Frequency registers for CHA, Fnco=1000MHz
        x"022100",
        x"022200",
        x"022310",
        x"024000",   -- NCO Frequency registers for CHB, Fnco=1000MHz
        x"024100",
        x"024200",
        x"024310",
        x"024400", -- NCO Phase for DDC B, Pi radians = 180 degree, Value = 32768 = 0x8000
        x"024580",
        x"002C00", --sysref position r/w
        x"002D00", --sysref position r/w
        x"002E00" --sysref position r/w

    For JM11,

    JM11
     x"0000B0",  ---reset adc x"0000B0",
        x"800300",   -- High speed ADC - returns 03h
        x"800400",   -- Chip ID register  - returns 03h
        x"0030FF", ----1000mvp-p for CHA
        x"0031FF",
        x"0032FF", --1000mvp-p for CHB
        x"0033FF",   
        x"004800",   -- Enable pre-emphasis if jesd is not working
        x"006000",  --Dual channel with no decimation mode& CHA samples INA±, CHB samples INB±.
        x"020000",   -- Disable JESD  
        x"006100",   -- Stop calibration
        x"02010B",   -- JMODE 11 is selected
        x"02021F", --Program KM1 (K-1); x"02021F" for K = 32, KM1 = 31 ; x"02020F",for K = 16, KM1 = 15
        x"020403",   -- Scrambler enabled, Signed 2's complement data format, ~SYNCSE used as ~sync
        x"020504",   -- JTEST Test pattern control register (Ramp Test mode selection)
        x"020600",   -- DID = 0
        x"020702", --FCHAR=k28.5
        x"0211F2",   --over range threshold 0
        x"0212AB",   --over range threshold 1
        x"02130F",   -- Enables overrange status output pins
        x"00621A", --enables background offset calibration
        x"806A00", ---returns the calibration status
        x"006B00",--cal pin config
        x"006C01",--cal soft trigger
        x"006E49", ---low power background calibration
        x"007000", ---calibration data enable
        x"002930", ---manual sysref calibration
        x"002970",---manual sysref calibration
        x"006101",   --- Enable calibration
        x"020001",   --- Enable JESD
        x"820800", ---reading the status of the JESD link
        x"021602", --digital channel binding
        x"022000",   -- NCO Frequency registers for CHA, Fnco=1000MHz
        x"022100",
        x"022200",
        x"022310",
        x"024000",   -- NCO Frequency registers for CHB, Fnco=1000MHz
        x"024100",
        x"024200",
        x"024310",
        x"024400", -- NCO Phase for DDC B, Pi radians = 180 degree, Value = 32768 = 0x8000
        x"024580",
        x"002C00", --sysref position r/w
        x"002D00", --sysref position r/w
        x"002E00" --sysref position r/w

    The clock configuration is as follows,

    Please let me know if any further information required.

    Thanks and regards

    Saisri

  • 0 in reply to Saisri Bhairi
    TI__Mastermind 20541 points

    Can you slow down the ADC clock frequency by half and try to see if the sync is stable that will tell us if there is signal integrity issues. Also try using the ADC without the sysref signal.

    Regards,

    Neeraj