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ADS2807 doesn't work normally!

Menglin Sun
Prodigy 50 points

Hello,
I use a ADS2807 in my FPGA based analog & digital mixed system, but it doesn't work normally. I choose  DC-Coupled ,Differential Driver circuit befor the AD input side just as the schematic shows.  The chip's temperature  rises to about 50°  no matter I give it  a clock or not (ADS2807's power consumption is about 720mW)  only  about 1 minute after it is powered.  Sampled data is almost totally wrong no matter  I give it AC or DC signal, though the DV(DataValid) pin's output wave is correct (about half cycle fall behind input clock). I wonder if the chip have already been damaged or  my operation or circuit have some problems.

 

  • 0
    TI__Mastermind 29220 points

    Hi,

    Regarding the temperature of the device, is the thermal pad of the package soldered to a thermal pad on the circuit board with adequate via connections to the ground planes?  Some ADCs will detect when the sample clock is not present and power down, but I do not know that this device will do that.  Some of our ADCs will exhibit power consumption that scales with sample frequency and many will have nearly constant power consumption over frequency, depending on the way the device was implemented.  If the power pad is not attached to a thermal sink into the circuit board, then the temperature may be correct.

    If the output data is not as expected, please check the common mode of the analog input signal at the input pins.  It should be about 2.5V, and the signal symmetrical about the common mode voltage when used with differential inputs.  How are you clocking the samples from the ADC into the next device, whether it is an FPGA or something else?  Are you using the DV as a clock?  The timing in the datasheet around the data valid looks like it should be ok to use the rising edge of data valid as a clock edge.  At the time that this device was developed it was also common to not output a clock with the sample data but rather specify the output data setup and hold time around the sample clock and use the sample clock to latch the data into the next device.  The min and max datasheet timings guaranteed for this device are relative to the sample clock edge.

    It could always be possible that a device has been damaged, but I don't usually start with that assumption when I do not see operation as i expect, especially if I have more than one board built up and the device behavior is consistent.

    Regards,

    Richard P.