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DAC80501: SPI Mode

JOHN MCCORKLE
Prodigy 150 points

Part Number: DAC80501

Two suggestions

1. On data sheets, please always state the SPI mode (0, 1, 2, or 3) required -- by any/all of your SPI parts -- i.e., if {CPOL, CPHA} = {0,0}, {0,1}, {1,0}, or {1,1}. How simple is that!  On the front page features, don't just say supports SPI, say supports SPI Mode-X.

2. On the DAC80501, you have a pin to select SPI or I2C.  Make that pin have analog states so that it can pick SPI mode 0, or SPI mode 1 or 2 -- i.e., reading the SPI data on a rising or falling clock edge.  If setup and hold times make it matter, give it enough resolution to select any of the 4 SPI modes e.g., via a single resistor and an internal current source or pull-up, or via a pair of external resistors to make a voltage divider between VDD and GND.

Questions for the DAC80501:

1) Which SPI mode is preferred, 1 or 2?

2) Why? Is the critical timing at the beginning when SYNC-bar goes low, or at the end when SYNC-bar goes high? Which setup or hold time is the one that matters in choosing the preferred mode?

3) If we run our SPI master in mode=0 or 4, and invert the clock and delay the SYNC-bar and the SDIN by the identical "gate delay" as the inverter, will it run at its max speed? or only with one of those modes, i.e., only mode=0 or only mode=4?

Thanks,

John

  • 0
    TI__Guru 57253 points

    Hi John,

    Thanks for those suggestions.  I will consider the first one as information we can add to the application section of the datasheet.  It generally comes up and we usually support two modes, as most devices only care about the setup edge and the latching edge.  Devices with readback functionality are a bit more complex, as most of newer devices have a fast-SDO mode where the data is setup on the SDO pin about 1/2 clock period early. 

    Your second suggestion is a bit more difficult, but probably available on some devices.  A multi-state input pin can be troublesome in the design, and most SPI controllers can support all 4 SPI modes.

    In regards to your questions:

    1. Either CPOL =0, CPHA =1 OR CPOL = 1, CPHA= 0 are supported by the device.  I would not say one method is preferred, but I generally use CPOL=1, CPHA = 0.

    2.  The only critical timing is to ensure that the falling edge of the first and last clock have enough margin from the falling or rising edge of SYNC (TSYNCS and TSYNCH). 

    3. Yes, it should run at it's max speed if you are manually inverting the clock in mode 0 or 3.  Assuming the edges comply with our timing limits (note our setup and hold time requirements), this will not be a problem.

    Thanks,

    Paul

  • +1
    Prodigy 150 points

    Paul,

    Many thanks.

    Regarding the multi-sate pin, yes most SPI controllers can support all 4 SPI modes, but at the same time, controllers require extra precious time to switch back and forth between modes and doing so adds programming/development/test costs. Inverting the clock is a pain because nano-seconds matter all the SPI lines have to go thru an equal propagation delay. Plus, for readback, that prop-delay matters and really slows things down. The worst issue for us is this... We have a board-stack with 10 SPI devices, 7 of which go thru an 8-way SPI programmable expander, and all but one (the DAC80501) read the data on positive edges. Using the expander just requires post-pending 8 address bits to the data stream going to a downstream device. We cannot simply hook the DAC up thru the expander because the expander addressing and flow-thru is itself positive edge clocked. The MOSI data stream flows thru the expander to the 7 downstream devices. Therefore, all the devices must work on the same clock edge. In one CS-bar cycle, data that ends up in the expander's address bits sets up the path/s for the next CS-bar cycle--i.e., sets up the CS-bar path (or paths for parallel MOSI data loading) and sets up the MISO path for readback from a single device. Delay is not a problem because the expander uses zero-delay FET switched paths. To make the DAC80501 work within the limits of this setup, we have to invert SCLK and not invert CS-bar and MOSI, which we do with XOR's so the prop delay and skew are very low. That works (i.e. the added delay does not matter) because we have no readback on the DAC80501. But the design would much easier and use less board space and fewer parts if the DAC simply had a mode-select pin. IMHO, it would be great if MFG's just made all SPI peripherals with a mode select capacity. I wish the expander had a mode select pin too.

    It is great that many of your RF switches now have a logic select pin. Same idea. Saves us from putting in gates to manage the polarity and timing. But way more impactful for SPI devices.

    Having a few address bits on SPI peripherals would also be great, (e.g.,BDA4710 attenuator https://documents.berex.com/BDA4710-V1.2.pdf), which could also be done with analog states on a single pin. A tiny little slow DAC that reads resistor value once at startup, and a table of 1% resistor values, how simple is that. :>)

    John