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JESD204C-IP with GTP transceiver

Etienne Drouin
Prodigy 60 points
Other Parts Discussed in Thread: ADC08DJ3200

Hi everyone!

I'm currently trying to make the JESD204C-IP work on an Artix 7 FPGA from Xilinx. The documentation says it should work at when I talked to TI employee they say the same thing. But when I change the IP from GTX to GTP a lot of signal change and the Transceiver wizard IP doesn't seem to be compatible with the rest of the JESD204C IP. The big problem is changing the qpll to a simple pll in the GTP transceiver. There is also changes on the DRP but those changes seem less difficult to overcome.

So my question is: Is there an example somewhere on how to instantiate the transceiver IP with GTP transceiver? This would help a lot thanks!

Étienne

  • 0
    TI__Guru 71526 points

    Hello Etienne,

    Please identify what TI device you are using in this circuit.  

    Thank you,

    ~Leonard  

  • 0 in reply to LeonardEllis
    Prodigy 60 points

    I would like to begin with a simple loopback circuit so no TI devices, but the goal is the make it work with an ADC08DJ3200

  • +1 in reply to Etienne Drouin
    TI__Intellectual 1760 points

    HI Etienne,

    We unfortunately don't have an existing example design for the GTP transceiver, but I expect it to be very similar to the GTX, because the 7000 series transceivers follow a common entity/port nomenclature. I understand that the primary difference will be a QPLL changing to a CPLL, due to which you will see extra ports that will need to be connected (CPLL ports per channel, as opposed to QPLL per Quad). However, that should be the only primary difference. The reference clock architecture will be the same, because unlike the ultrascale architectures, the reference clock buffer is part of the transceiver IP that is created by the wizard.

    It is possible that Xilinx has created additional glue logic around the DRP port for the Artix7 GTP. This is used for extra register writes that may be needed for proper initialization of the transceiver (usually as a post Silicon fix).

    I will request you to kindly try the following steps:

    1> Use the gtx_8b10b_rxtx.sv file as a reference for how the transceiver is connected to the ports of the mgt_8b10b_wrap module

    2> Create a gtp_8b10b_rxtx.sv file with the same ports, but with a GTP instance. Most of the connections will remain the same, except that you will have CPLL ports. In addition, the number of active lanes may be different from the GTX reference design (which has 8 lanes).

    Please run a simulation of the full IP (in loopback mode) after these changes. Both the GTX and GTP based designs should show the same link behavior (except that the number of clock cycles may be different due to different init times between the two transceiver models).

    Regards,

    Ameet