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TSW1400EVM: Thinking about Purchasing For Lab

Ryan Brady
Prodigy 10 points

Part Number: TSW1400EVM
Other Parts Discussed in Thread: DAC5681EVM

Myself and my lab group are interested in purchasing the TSW1400EVM and interfacing it with the DAC5681EVM. 

We have some specifications, and I am wondering if the combination of these devices can accomplish our goals:

  1. Generating arbitrary waveforms of 10 microseconds long at 1 Gsps.
  2. +/- 1V amplitude with computer control
  3. Generation of sine waves that can sweep from 100MHz to 200MHz
  4. Triggering rate of 100kHz
  5. Record Length of 10,000 samples
  6. What is the update time?
  7. Are both devices needed or can we send a waveform directly to the DAC5681EVM from a computer without the TSW1400EVM?
  • 0
    TI__Mastermind 24450 points

    Hi Ryan, please see my answers to each of your questions below.

    1. Yes, this is possible. This will be a 10k point signal. (1GSPS * 10*10^-6 seconds) = 10k samples.
    2. You can use our software to scale the input codes to any amplitude under full scale if desired. Optionally, you can use python or MATLAB to create the input pattern as a csv file and upload this to our software, but this is not a "real-time" application. If you want to change the input scale as a response to some control loop you will have to develop FPGA firmware for LVDS interface and load using intel quartus.
    3. Our software doesn't allow for creating chirp signals. I imagine something in python or MATLAB exists for creation of chirps. Once created, you can upload the custom pattern.
    4. The FPGA cannot trigger at 100kHz. 
    5. Yes
    6. The update time is going to be limited strictly by the software controlling the FPGA mainly being how fast the new data can be loaded into HSDC Pro (for a 10k point signal, it should be around ~0.25 seconds) as well as the DAC latency (negligible when compared to 0.25 seconds)
    7. Both devices are needed. The computer loads the high speed pattern to the FPGA over USB and then the FPGA sends the data to the DAC over the LVDS interface. There is no way to generate waveforms at these speeds without an FPGA for a traditional high speed DAC.

    I would suggest for you and your team to look into configurable DDS (direct digital synthesis) devices. What you are talking about may be much simpler to achieve using a DDS part. Unfortunately TI doesn't offer any DDS devices at this time. A quick search online should get you started.

    Thanks, Chase 

  • 0 in reply to Chase W
    Prodigy 10 points

    Chase,

    Great, thank you so much for the help. I have one more inquiry then: what is the maximum trigger rate of the FPGA?

  • 0 in reply to Ryan Brady
    TI__Mastermind 24450 points

    My guess is around 1 Hz for TSW1400EVM, there are a lot of factors such as computer speed but the main drawback is the USB2.0 interface for the FPGA.

  • 0 in reply to Chase W
    TI__Mastermind 24450 points

    Note that in the original post, instead of every 0 25 seconds it's moreso like once every 1 second. I was thinking of a different board when I answered that question this morning. 

  • 0 in reply to Chase W
    Prodigy 10 points

    Hi,

    Could you explain the triggering a bit more? 1 Hz seems very slow, especially since these devices are designed for high-speed data acquisition. Thanks!

  • 0 in reply to Ryan Brady
    TI__Mastermind 24450 points

    For ADC, our evaluation platform is designed for taking deep captures but not for real time evaluation. Our software triggers the FPGA to begin storing captured data into memory on our FPGA evaluation board (whether the trigger is simply pressing the Capture button or if using external hardware trigger). The software has to load the memory off of the TSW1400EVM and display data into the HSDC Pro window. For evaluation of DAC, the opposite is true. The pattern must first be loaded into TSW1400EVM memory. Afterwards the trigger will begin data output from FPGA to DAC. The out of box evaluation platform is focused on testing performance of our devices in deep captures/patterns and not necessarily intended to support testing on edge cases. The slow trigger is a result of the software and there is no way to speed it up.

    Thanks

  • 0 in reply to Chase W
    Prodigy 10 points

    Hi,

    Thank you very much for the response. From my understanding so far, it seems as though the FPGA triggers the DAC at 1Hz. Would it be possible to trigger the DAC externally? Essentially we would use the TSW1400EVM to create and load the waveform to the DAC, but use a trigger solely on the DAC to synchronize the output with our other equipment.

    Thanks.

  • 0 in reply to Ryan Brady
    TI__Mastermind 24450 points

    Ryan, what do you mean by sychronize with external equipment? If you are referring to 10MHz reference locking the DAC output to other test equipment simply providing a clock into the DAC from a source which is reference locked is all that is needed. The DAC output waveform that is loaded to the FPGA will repeat continuously so I am not sure what else you are referring to by synchronize other than a 10MHz ref lock.

    Thanks

  • 0 in reply to Chase W
    Prodigy 10 points

    Hi,

    In many experimental setups, precise timing and synchronization are crucial to ensure accurate measurements and data acquisition. The triggering rate of the DAC is necessary to control the timing of the output waveform, which can be essential when coordinating the DAC output with our other pieces, such as our cameras or pump-probes. Is this the process described by 10MHz reference locking?

    Thanks.

  • 0 in reply to Ryan Brady
    TI__Mastermind 24450 points

    10MHz reference locking ensures the reference oscillator between any pieces of test equipment (reference oscillators are used to generate all clocks in test equipment's system) will be perfectly synchronized, meaning signals, mainly the frequency aspect of signals, are measured with exactness instead of measuring as a frequency which is close to another frequency. 240MHz will read as 240MHz when equipment is reference locked where the same 240MHz may read as 239.898MHz when the equipment is not reference locked.

    Can you share a drawing of roughly your signal characteristics and trigger timing in MS paint or by hand? I'm having a hard time understanding what exactly you are wanting to achieve still and hope this will help us understand.

    Thanks

  • 0 in reply to Chase W
    Prodigy 10 points

    Chase,

    Apologies for the delay in my response. I have attached an image of the basic design schematic. Please let me know if you have any questions. 

    experimental_setup.pdf

    Thanks Again,

    Ryan

  • +1 in reply to Ryan Brady
    TI__Expert 3950 points

    Hey Ryan, 

    The FPGA to PC interface is the main limitation. For DAC devices, the TSW1400 along with HSDC pro is designed to upload a single pattern into FPGA memory and send it to the DAC. It will send it to the DAC at the actual sample rate of the DAC (1 GSPS in your case). It will wrap around as it reaches the end of the samples and continue to repeat over and over again. This allows evaluation of key DAC performance characteristics like SNR, SFDR, phase noise, etc. 

    If you want to dynamically change the pattern that is sent to the DAC you would need to write custom FPGA firmware to do this. The FPGA to PC interface is not very fast and therefore sending real-time sampling data to the FPGA at the types of rates you're talking about will not be possible. 

    Regards, 

    Matt