DAC81402: EOS protection design

Davide Tosatto

Part Number: DAC81402

Hello everyone,

I seek assistance properly designing the electrical overstress protection circuit for my DAC81402.

Following the EOS protection scheme shown in its datasheet, I choose the TVS D3 with a Vclamp=67V, the ferrite bead FB1 with a 120Ω @100MHz, the diodes D1 and D2 have a forward voltage Vf=0.7mV.

How high should R1-R2 (and R3) be to sustain ESD pulses? For example, I can consider an 8 kV IEC ESD (contact discharge).

In the datasheet it is assumed a R1=10Ω, how has it been chosen? Would it be enough for this application?

Thank you,

Davide Tosatto

over 1 year ago

0 Davide Tosatto over 1 year ago

Prodigy 70 points

Note: in my application AVDD=+15V and AVSS=-15V. Furthermore D1 and D2 Vf=0.7V, not mV .

0 Paul_Frost over 1 year ago in reply to Davide Tosatto

TI__Guru 53583 points

Sanjay will help here.

+1 Sanjay over 1 year ago in reply to Paul_Frost

TI__Expert 3810 points

Davide,

Here is few things that needs to be taken cared of -

1. D3 clamp voltage should be much lower. As you are using supply ±15V (AVDD/AVSS).

2. as shown in app section of the data-sheet, please use the D4 and D5 TVS didoes for HV supplies also.

3. idea is to reduce the pin voltage (with help of TVS D3) and pin current surge (with help of D1, D2 and FB1).

4. R1,R2 and R3 can be kept ~10 ohm.

Note : as per data-sheet description, 10 ohm value came up with assuming 80mA current in the VOUT pin (whenschottky diode clamps VOUT to ±1.5 V from rail)

Thanks,

Sanjay

0 Davide Tosatto over 1 year ago in reply to Sanjay

Prodigy 70 points

Thank you very much for your suggestions!

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DAC81402: EOS protection design