The pseudo code example in section 10.1.7 puts the SYNC outside of the loop. To paraphrase slightly (and omitting the CS commands):
- Send SDATAC command (16h) to prevent the new data from interrupting data or register transactions;
- Write the respective register configuration with the WREG command (40h, 03h, 01h, 00h, 03h and 42h)
- Send the SYNC command (04h) to start the ADC conversion;
- Loop:
- Wait for DRDY to transition low;
- Send the RDATA command (12h) and read the result
Is that really right? In reading the rest of the documentation, one gets the impression that in SDATAC mode, you need to to issue a SYNC command to initiate each conversion
I suspect the pseudo code should put the SYNC command inside the loop, like this:
- Issue SDATAC for single-sample mode
- Configure via WREG
- Loop:
- issue a SYNC command to start the conversion
- wait for DRDY- to transition low
- read the data via an RDATA command
Is that correct?
