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AFE5809: Questions for AFE5809 I/Q mode usage and switching problems

Jacky Wang(QD)
Genius 11600 points
Part Number: AFE5809

Hi Team,

Customer is evaluating for our AFE5809 and having below questions about LVDS data output mode between I/Q and ADC, please help to answer:

  1. In customer’s configuration, LVDS serialized setting is 16bit, but for ADC data is 14bit. For FPGA LVDS receiver, does it will affect the switching between 16bit and 14bit LVDS? Or we need to make the training for LVDS?
  2. What’s the time delay for I/Q LVDS to ADC LVDS mode?
  3. Regarding to I/Q, filtering, decimation factor etc. parameters, which one we can make the configuration in advance, and no impact from I/Q and ADC mode switching?
  5. If we configuration the I/Q parameter in advance, what’s the time delay for LVDS data output after other configurations?
  6. Do we have any suggestions for I/Q and ADC LVDS data mode switching and concerns in such case?

Thanks.

  • 0
    TI__Expert 7020 points

    Hi Jacky,

    Please find the response inline:

    1. In customer’s configuration, LVDS serialized setting is 16bit, but for ADC data is 14bit. For FPGA LVDS receiver, does it will affect the switching between 16bit and 14bit LVDS? Or we need to make the training for LVDS? Will they change serialization factor from 16x to 14x while switching between the demod and normal mode? If yes then they have to perform training again.
    2. What’s the time delay for I/Q LVDS to ADC LVDS mode? I could not follow this question, can you please elaborate? Are you looking for the latency numbers, if so, the data sheet provides the device latency numbers at multiple places for various mode. Please refer to the datasheet diagrams.
    3. Regarding to I/Q, filtering, decimation factor etc. parameters, which one we can make the configuration in advance, and no impact from I/Q and ADC mode switching? They can keep the demod enabled and bypass the down conversion, bypass decimation filter and set decimation factor to 1 to get normal data data
    4. If we configuration the I/Q parameter in advance, what’s the time delay for LVDS data output after other configurations? They have to apply TX_TRIG to get valid demod data after configuring it, datasheet shows the latency in demod, refer to timing diagram in the datasheet.
    5. Do we have any suggestions for I/Q and ADC LVDS data mode switching and concerns in such case?In case if they disable the demod, then complete demod setting has to be configured again.

    Thanks & regards,

    Abhishek