Hi
Since in my application it is not possible to reduce the analog input channel source impedance arbitrarily, I need some more details:
1. The Datasheet recommends to reduce CCLK, for a analog input channel source
impedance greater than 2k. If I use the internal oscillator, I cannot reduce
CCLK. Does it also help to increase the division factor DF, to reduce DCLK
instead of CCLK?
2. Does the mentioned 2k source impedance refer to the maximum conversion
frequency of 50kHz? It is unclear, under what conditions this source impedance
was calculated: - What is the remaining LSB fraction that was provided and what
is the ADC input series resistance?
We use a 14 bit converter and require at least 12 effective bits. Thus, I need this information for a proper design.
Thank you very much for any help!
Timon Meier