ADS8556: About REF_IO output abnormal

Hi Jimmy,

Can you provide a schematic?  In the second screen capture, the REFIO is coming up ahead of the REF_EN and that should not be able to happen.

Hi Tom,

pls refer below. Do you have any suggestions here? thx 

Does toggling the RST pin have an impact on the issue?

Hi Tom,

Do you mean Reset? I have no idea why happen and how to solve it. 

Yes, does toggling RESET resolve the issue?

Hi Jimmy,

We're asking if using the RESET pin or STDBY pin clears this behavior and sets REFIO to the correct voltage?

Thanks,

-Cole

I confirm with customer. thx 

Hi team,

Customer use STDBY pull low then Pull high will let 5V change to 2.5V.

But customer asking why abnormal 5V out?  

Hi Cole,

Customer used STDBY pin that could set REFIO to the correct voltage. But which reason causes it?

Hi Cole,

Any reply? thx 

When the customer reboots the system. the abnormal will occur. 

Cole is on Holiday until the 24th.

Hi Tom,

Any other people can reply to the issue? thx 

By the little information provided, the assumption is that you are not getting a proper POR.  Exactly why that is we cannot tell, but since toggling the reset or standby clears the issue you should implement that as part of the initialization sequence.

Hi Tom,

But customer replies to the system reboot will cause this issue again. 

What information can I provide to help clarify the problem?

Hi Jimmy,

Would it be possible to recapture the waveform with 470nF capacitor on REFIO or higher? 

Right now, I don't see any good reason besides the signal sequencing is switched between the good and abnormal waveform. Given that design uses very specific values on these capacitors to do power up simulations, I'd recommend switching to the higher value regardless.

Given the data does prove this is only during power up, we need to focus on the differences between power up and coming out of standby, which is the applied voltage ramp rates. Alternatively, it might be good to insert delay before applying REFEN just to see what happens.

Best,

-Cole

Hi Cole,

The customer replies the same result. But they saw some improved methods.
If REFEN's rising time is fast. the issue will be solved. I checked the schematic that found VCC and EN is connected.

Do need some sequence on VCC and EN?

Hey Jimmy,

Good find. We have a 100k ohm pull up on our reference EVM and do sequence that GPIO. They should see if a pull-up helps or hinders the success rate.

And I assume VCC = BVDD (or D3.3V) and EN = REF_EN/WR?

Its an interesting result, I would have thought making it slower would make it more likely. We currently don't have any information on sequencing so I'll have to ask the team on that.

Best,

-Cole

Hi Cole,

Customers use external power to test this board. when the power supply rising time slowly(around 40 ms) that the issue will happen. 

But no limitation in the datasheet. customer can not accept it. Can you please collaborate with internal colleagues to replicate this phenomenon?

Hi Jimmy,

Thanks for the clarification.

The team has not seen this before and is not exactly sure what the issue could be. There's a possibility there is a power supply sequencing or specification problem but we can't see this. As a result, we need some more data from the customer. Can they provide AVDD, HVDD, and BVDD in addition to REF_IO on the same oscilloscope waveform? 

Best,

-Cole