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ADC3424: PSRR

Part Number: ADC3424
Other Parts Discussed in Thread: , TPS7A20

Hello,

I'm looking to use the ADC3424 and currently looking at the power supplies I provide for it. From Figure 121 of the datasheet I notice PSRR is generally 30-40dB across the frequency range. Can you confirm if this applies only to the analogue supply (AVDD) or will noise on the digital supply (DVDD) have the same effect? I don't see any mention of PSRR anywhere apart from Figs. 121 and 122.

I plan to supply AVDD with a nice clean 1V8 supply, trimmed with LDO and ferrite beads. I had hoped just to power the digital supply pins from the rail powering the FPGA that will be communicating with the device, but at present this is a noisy supply direct from SMPS.

If the digital supply needs to be low-noise I'll change the design, but obviously would rather not do so if it has no effect.

Can you please advise.

Thanks,

Gordon.

  • Hi Gordon,

    Figure 121 in the datasheet gives the Power-Supply Rejection Ratio over input frequency for the ADC3424. This measurement encompasses both the AVDD and DVDD.

    Figure 122 is showing an input frequency of 30.1 MHz with a 3 MHz spur with amplitude of 50mVpp injected on AVDD. A noise spur shows up at 3 MHz that is reduced by the PSRR.

    If the digital supply is noisy as you mentioned, then it would be ideal to use another solution to optimize ADC performance. On the ADC3424EVM, we use a TPS7A4700 RF LDO, a TI part designed for applications where clean voltage rails are critical to maximize system performance. 

    Regards, Amy 

  • Hi Amy,

    thanks for that. I have the TPS7A20 elsewhere in the design so I'll probably just use this again here. Probably not quite as good as the TPS7A4700, but good enough on both noise and supply rejection I think, and it'll have ferrite beads on input and output to minimise any high frequency issues.

    Thanks for your replay - appreciated.

    Gordon.