• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 46 subscribers
  • Views 125 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC32RF42: ADC32RF42

Erdal G
Prodigy 50 points
Part Number: ADC32RF42

Hi,

I have 2 questions, First one is a general question not exactly related with the part and I'd appreciate if you can give an answer. Since sysref frequency is way smaller than the device frequency of an FPGA or ADC32RF42, why do we care about setup and hold time violations? Doesn't device clk rising edges sample sysref signal many times(since sysref signal is way slower than sampling clocks) when sysref is high?

Second question is related with the part ADC32RF42. On page 46 of the datasheet, table 14 shows the data alignment when the adc is used in 12 bit bypass mode. It looks like no data is sent through lanes 2 and 3 according to table 14. Is this correct? If so then will I need 1.5Gs/s x (64/5)x(10/8)=24Gb/s interface? Since only 2 lanes are active(according to table 14) I need a lane rate of 12Gb/s which means I can not use a kintex 7 FPGA Disappointed. Am I correct? Can you please enligthen me..

  • +1
    TI__Genius 13031 points

    Hi Erdal,

    For the first question, on page 10 of the datasheet, the setup and hold time is "referenced to clock rising edge". This means that the data must be sampled within this window to be valid. 

    As for the second question your calculation is correct, so a capture solution will need to be able to keep up with this output data rate to use. 

    Regards, Amy