Hi,
I have 2 questions, first one is a general question related to jesd204 interface and I'd appreciate if you can answer it. Since sysref frequency is way smaller than device clk frequency of an FPGA or ADC32RF42, why do we need to worry about setup and hold violations during device clk sampling sysref? Doesn't sysref signal stays high for many device clk rising edges due to large difference in the frequencies of sysref and device clk?
Second question is related with ADC32RF42 in bypass mode. On page 46 of the datasheet according to table 14, when ADC32RF42 is used in 12 bit bypass mode, data is only sent through lanes 0 and 1. Is this correct? If so then adc will need 1.5Gs/s x (64/5) x (10/8)=24Gb/s interface speed and since 2 lanes are in use lane rate of 24Gb/s / 2= 12Gb/s will be required which means I won't be able to use a kintex 7 FPGA. Please correct me if I am wrong.
