• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 46 subscribers
  • Views 547 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC 1258 Register read problem

Sathyanarayanan Kuppuswamy Natarajan65234
Prodigy 40 points
Other Parts Discussed in Thread: ADS1258

 

Hi Everyone,

 

            I am building an ARM board,  interfaced with external ADC (ADC 1258 ). I took the schematics from ADC EVM document and followed it my circuit. I have already purchased an EVM board and tested my code with it. It works fine with EVM board.

 

But When I try the same in the integrated board that I built with ADC , it is not working. When I read the register values of ID register or Config registers, I am getting random values. Sometimes I get the expected results too. But its not consistent.

 

I have used Osciallocope and verified the following.

 

1. To check the hardware power up status , I have checked the CLK IO pin and found that I get the waveform at the expected frequency.This shows that my hardware is excited propely.

 

2. Checked SCLK, DIn,Dout pins. In Dout pin I am seeing random data values. All other pins shows the expected signals.

 

Attached the schematic of the ADC circuit with this post.

 

Please let me know what could be the possible reason to get random values in Dout pin of ADC.

 

  • 0
    Prodigy 40 points

     

    Hi Everyone,

     

                I am building an ARM board,  interfaced with external ADC (ADC 1258 ). I took the schematics from ADC EVM document and followed it my circuit. I have already purchased an EVM board and tested my code with it. It works fine with EVM board.

     

    But When I try the same in the integrated board that I built with ADC , it is not working. When I read the register values of ID register or Config registers, I am getting random values. Sometimes I get the expected results too. But its not consistent.

     

    I have used Osciallocope and verified the following.

     

    1. To check the hardware power up status , I have checked the CLK IO pin and found that I get the waveform at the expected frequency.This shows that my hardware is excited propely.

     

    2. Checked SCLK, DIn,Dout pins. In Dout pin I am seeing random data values. All other pins shows the expected signals.

     

     

    Attached the schematic of the ADC circuit with this post.

     

    Please let me know what could be the possible reason to get random values in Dout pin of ADC.

     

  • 0 in reply to Sathyanarayanan Kuppuswamy Natarajan65234
    TI__Mastermind 43915 points

    Hi Sathyanarayanan,

    The register contents from the ID register may not be the same on the EVM board as on your board. It may be that the EVM board uses an older Rev. of the part compared to the specific sample that you are using on your proto board. When debugging, I would recommend you try reading back the contents of the ID register as they are factory fixed (depending on the REV of the part) and will not change if written to. Once you can verify that you always read back the same contents from that register, you can more onto the converter itself. Therefore, you should be able to write 0x49 to read the ID register and always ready back the same contents. If not, when the read back ID contents are corrupt, I would look to see if a possibly a /DRDY pulse is being initiated midway through the ID register readback.

    Secondly, are you sharing the SPI bus of the ADS1258 with other devices? The reason I ask is if you look at Figure 57 on page 30 of the data sheet, you will see note 3 which mentions that after a DRDY falling edge, there should not be SCLK activity on the line until /CS is low and you read back data. The reason being, when /CS is high, the SCLK line is still connected so if clocks are sent to the device, the output word will begin to be clocked out. However, since /CS is high, the DOUT line will be 3-state, so the data will be clocked out but you will not be able to see it on the line. Therefore, you are essentially just losing the MSBs. Therefore, it is important to not have SCLK activity after DRDY goes low unless your ready to read back the data when using the Channel Data read direct (No command). If you are using the Register and Channel data read (Register Format in Fig 58), you do not need to worry about losing the MSBs.

    Those are two places to start looking. Let me know if you make any progress.

    Regards,

    Tony Calabria