ADC32J25: JESD204B Configuration

Andrew Baek

Intellectual 915 points

Part Number: ADC32J25
Other Parts Discussed in Thread: LMK04828,

Hello,

We now have the board built and are in the process of bringing up.

The schematic was reviewed before but wanted to double check.

on Sheet 18
- MGTREFCLK0P/N is 160 MHz device clock to the FPGA (receiver)
- FPGACLK1P/N is 8 MHz SYSREF to the FPGA
- ADCCLKP/N is the 160 MHz clock to the ADC (ADC32J25IRGZT, transmitter)
- SYSREFP/N is the SYSREF to the ADC
- Should they be all LVDS?
  - If so I should remove R414 and R415
  - Should I also update R418 and R419 to 0 Ohm?
  - Do I still need R346 and R347 for LVDS going to the FPGA?
Previously the following was mentioned
- The lane rate = (Fs * 10 * F) / S. With LMFS = 2221, this is (160M * 10 * F) / 1 = 3.2Gbps. If you use a value of 20 for K, your SYSREF = Fs / (N * K), where N is any whole integer. If N = 1, your SYSREF = 8MHz.
- Per the JESD204B standard, the following two equations must be met:
  
  1 < K < 32
  
  17 < F*K < 1024
  
  Since your F is 2, K will need to be at least 9. The larger value you use for K, the more buffering you provided for the data, but the larger the latency will be. Some parts only allow certain values of K to be used.
N doesn't seem to be tied to any parameters. Then K becomes arbitrary. How do I determine N?

The schematic was reviewed but could you take another look at

Sheet 2: SYNCP_ADC & SYNCM_ADC
- are generated as 3.3V CMOS
Sheet 3: FPGACLK1P/N: SYSREF from LMK04828
- LVDS
Sheet 5: DAP/M_ADC, DBP/M_ADC, and GTREFCLK0P/N
- All LVDS
Sheet 15: ADC32J25IRGZT
Sheet 18: LMK04828

I think all of the differential signals are LVDS except SYNCs.

I would appreciate if you could take another look and confirm on the circuits and terminations.

Regards,

Andrew

1067.fibersense_v1p23.pdf

over 2 years ago

0 Amy over 2 years ago

TI__Genius 15321 points

Hi Andrew,

I will check into this. Just a heads up, the response may be delayed due to the holiday.

Regards, Amy

0 Chase W over 2 years ago

TI__Mastermind 23860 points

Andrew,

Yes, all clocks and SYSREF should be LVDS.

N is an integer such that the SYSREF frequency falls on a multi-frame boundary. If you want to run the SYSREF frequency slower, it must be an integer multiple of the maximum SYSREF frequency (Fs/K). In the example above, if you set N=2, then the new SYSREF frequency will be 4MHz. This still lands on a multi-frame boundary.

The only worry I see with your schematic is this device uses a differential SYNC. SYNCP and SYNCN should be DC coupled with VCM at 0.95V.

Typically in cases like this, an LVDS to LVPECL translation is performed using a voltage divider. What is the IO level for these FPGA pins?

Thanks, Chase

0 Andrew Baek over 2 years ago in reply to Chase W

Intellectual 915 points

Hi Chase,

My apologies for delay. was traveling.

SYNCP~ and SYNCM~ are 3.3V CMOS from regular FPGA pins.

Would it still work for 1.3V VIH?

Thank you,

Andrew

0 Andrew Baek over 2 years ago in reply to Andrew Baek

Intellectual 915 points

Hi Chase,

Could you take a look at SYNCP/M~ signals on the schematic?

They are generated by the regular FPGA pins with 3.3V CMOS.

Also for Class 1 JESC, as I understand, SYNC~ is not used. Instead SYSREF is used.

Is this correct?

Thank you,

Andrew

0 Andrew Baek over 2 years ago in reply to Andrew Baek

Intellectual 915 points

Hi Chase,

Btw I found the following quote from my previous thread on schematic review of the current design with ADC32J25

"SYNC is basically a DC signal in the JESD204B standard and should not have the AC caps. The 100 Ohm termination is also not needed."

I think that was the reason I kept the design the way it is now.

Please let me know.

Andrew

0 Andrew Baek over 2 years ago in reply to Andrew Baek

Intellectual 915 points

Hi Chase,

Can you take a look at this or try it?

DCLKout0 is the reference clock to the FPGA at 160 MHz

and SDCLKout1 is the SYSREF to the FPGA at 8 MHz

I probed both. I observed a 160 MHz signal at DCLKout0 but there is no signal at SDCLKout1.

Could you see if I am missing something for the SYSREF output?

Thank you,

Andrew

LMK04828b_v071623c.tcs

0 Andrew Baek over 2 years ago in reply to Andrew Baek

Intellectual 915 points

I have tried a few different configurations but still no SYSREF on SDCLKout1.

I was just looking at the datasheet. Do I need to pulse or toggle the SYNC (Pin 6) on LMK04828 to generate the SYSREF signal?

Thank you,

Andrew

0 Chase W over 2 years ago in reply to Andrew Baek

TI__Mastermind 23860 points

Hi Andrew,

Sorry for the delay. I was out sick earlier this week and have returned today. Please find my comments below.

Andrew Baek said:
SYNCP~ and SYNCM~ are 3.3V CMOS from regular FPGA pins.

Would it still work for 1.3V VIH?

No, this will not work. The device is expecting a DC couped differential signal for SYNC with max voltage applied up to AVDD + 0.3V. This means either SYNC pin should only see a max of 2.1V.

Andrew Baek said:
Also for Class 1 JESC, as I understand, SYNC~ is not used. Instead SYSREF is used.

Partially correct, JESD204B subclass 1 uses SYSREF for deterministic latency, but still uses SYNC for beginning CGS (code group synchronization) phase of bring up. The ILAS (Initial lane alignment sequence) phase will be driven by SYSREF as the ILAS falls on a LMFC boundary (which in subclass 1 is aligned to SYSREF).

Andrew Baek said:
Hi Chase,

Can you take a look at this or try it?

DCLKout0 is the reference clock to the FPGA at 160 MHz

and SDCLKout1 is the SYSREF to the FPGA at 8 MHz

I probed both. I observed a 160 MHz signal at DCLKout0 but there is no signal at SDCLKout1.

Could you see if I am missing something for the SYSREF output?

Thank you,

Andrew

LMK04828b_v071623c.tcs

We will have someone from the clocking team look at this shortly.

Andrew Baek said:
I was just looking at the datasheet. Do I need to pulse or toggle the SYNC (Pin 6) on LMK04828 to generate the SYSREF signal?

From my understanding, if you are in pin-pulse mode, you will need to toggle SYNC on LMK04828 to generate a burst of SYSREF signal. If you are in continuous SYSREF mode, this is not necessary. Again, someone from the clocking team will review this for you.

Regards, Chase

0 Andrew Baek over 2 years ago in reply to Chase W

Intellectual 915 points

HI Chase,

I started another thread on LMK04828 where I'm trying to see if LMK04828 is set up correctly.

Below is the register file with the steps to set up the SYSREF generation (Lines 137 thru 147.

Still not seeing the SYSREF output from SDCLKout1.

In the meanwhile, all of the control signals including SYNC~ are coming from 3.3V pins,

So they are above AVDD (1.8V) + 0.3V. I can try to read back.

Would they have damaged the ADC? Would they not work at all, even if we slow down significantly?

I will try to see if there are ways to rework but am preparing for a board spin.

Thank you,

Andrew

0 Andrew Baek over 2 years ago in reply to Andrew Baek

Intellectual 915 points

I have missed the file. Here it is.

Thank you

Fullscreen HexRegisterValues_072023a.txt Download

0 Andrea Vallenilla over 2 years ago in reply to Chase W

TI__Genius 10995 points

Hello Andrew,

I was able to replicate your issue on the bench but I'm still struggling to understand why we are both seeing the same issue. I should have this resolved by next week and I can get back to you then. Also, following up on Chase's response, what he said is correct. You can generate the SYSREF signal by either toggling the SYNC pin or using the SYSREF pulser, not necessarily both. Also is your question/statement below:

Andrew Baek said:
Below is the register file with the steps to set up the SYSREF generation (Lines 137 thru 147.

Still not seeing the SYSREF output from SDCLKout1.

related to the same issue you mentioned here:

Chase W said:
I observed a 160 MHz signal at DCLKout0 but there is no signal at SDCLKout1.

Thanks!

Best,

Andrea

0 Andrew Baek over 2 years ago in reply to Andrea Vallenilla

Intellectual 915 points

Hi Andrea,

Here's the TICs pro file I used to export the register values.

Thank you,

Andrew

LMK04828b_v072123a.tcs

0 Andrea Vallenilla over 2 years ago in reply to Andrew Baek

TI__Genius 10995 points

Hello Andrew,

I was able to solve your problem. From the second file you attached, you need to:

1) Set SYNC_DISSYSREF = 0 and then toggle SYNC by setting 0x143 = 31 and 0x143 = 11. This resets the dividers and aligns your outputs.

2) Set 0x144 = FF. This disables the outputs from being resynchronized from a SYNC event.

3) Set 0x143 = 11. This sets the device to obtain the SYNC from the SYNC pin generated via SPI.

4) Set 0x139 = 03. This makes the SYSREF_MUX output a continuous SYSREF so you will be able to see a signal at any time you probe the pin. If you don't want to see use a continuous signal, but still see the signal when you probe it, you need to set your scope to trigger on the rising edge of your signal.

I have attached the .tcs file that works on my end. You should load it and it should work.

LMK04828_JESD204B_Config_Cust.tcs

Hope this helps. Good luck!

Best,

Andrea

0 Andrew Baek over 2 years ago in reply to Andrea Vallenilla

Intellectual 915 points

Hi Andrea,

The 8-MHz Sysref is working after following your suggestions!

Also attached below are the .tcs (which is the same as yours) and the .hex file I used (basically exported from TICs Pro and added your suggested commands after 0x1FFF53

0820.LMK04828_JESD204B_Config_Cust.tcs

Fullscreen HexRegisterValues_072423c_ti.txt Download

I will now try to get the ADC working with JESD204B.

Thank you so much,

Andrew

ps: I would like to keep this for a few more days while I am trying to get the JESD204B working with the ADC

0 Andrew Baek over 2 years ago in reply to Andrew Baek

Intellectual 915 points

Hi Andrea,

Could you take a look at the notes and the schematic?

Mainly I'm trying to see if the signaling types are consistent between LMK04828 and ADC32J25

ADC32J25 is expecting ADCCLKP/N and SYSREFP/N to be LVDS
On LMK04828, those signals are designed to be LVPECL. I can update the resistors.

Thank you,

Andrew

notes 072423a.pdf

6318.fibersense_v1p23.pdf

0 Andrea Vallenilla over 2 years ago in reply to Andrew Baek

TI__Genius 10995 points

Hello Andrew,

Here are my suggestions on your schematic:

Instead of powering down CLKout10_11, I would power down CLKout8_9 and use CLKout10_11 for your 100-MHz outputs. Since 160-MHz and 100-MHz pins are relatively close, placing them as far apart from each other as possible will minimize crosstalk.
VCC9_CP2 0.1-uF cap next to the ferrite bead should be placed to the left of the ferrite bead. From Figure 41 on the DS (included below), the 0.1uF to the right should only be added for phase detector frequencies (PFD) < 50-MHz, which is not your case (your PFD is 80-MHz).

To any SPI lines, it's a good rule of thumb to add a series resistor on those lines (a 10-Ω resistor should suffice) close to the SPI pin. That applies to CLKin_SEL (pins 58 and 59), STATUS_LD (pins 31 and 48), RESET (pin 5), SYNC (pin 6), SCK (pin 19), and SDIO (pin 20)
If you are planning to change the termination to LVDS, you should use the below setup (Figure 30 on LMK04828 DS) for the ADC and SYSREF to the ADC since both inputs to the ADC require an external termination.

For CLKout6, since it's LCPECL, you need the below termination:

The termination for CLKout8 and CLKout9 should be on the receiver side, not the LMK04828.

I'll let Chase comment on the rest of the schematic.

Best,

Andrea

0 Andrew Baek over 2 years ago in reply to Andrea Vallenilla

Intellectual 915 points

Hi Andrea,

Thanks again for your review.

Currently the board has been built so I'll try to get it working as much as possible, and follow your recommendations in the next board spin.

As for ADCCLKP/N and SYSREFP/N, the ADC is designed for LVPECL and so is LMK04828.

So I think it should be okay.

With Sysref working, let me see if I can capture some data from ADC.

My concern is the control signals are coming from 3.3V FPGA pins, above 1.8V + 0.3V.

Let me get back to you once I try.

Regards,

Andrew

0 Andrea Vallenilla over 2 years ago in reply to Andrew Baek

TI__Genius 10995 points

Hello Andrew,

All the suggestions I made are more recommendations rather than requirements to make the part work, except for the CLKout6, not sure if that termination you have will allow you to see a LCPECL signal. If you are seeing your desired output, then I would not worry in terms of the LMK04828.

For the LVPECL signal coming out of the LMK04828 to the ADC, that should not cause any issues on either part. In fact, the ADC can handle an LVPECL clock and because of the higher swing, it'll actually improve your ADC performance. In fact, I would recommend that termination to the ADC if you don't mind higher power consumption. Hope this helps.

Best,

Andrea

0 Andrew Baek over 2 years ago in reply to Andrea Vallenilla

Intellectual 915 points

Hi Andrea,

I had been traveling, and am back to this.

I have verified that the FPGA is able to send the register values to the ADC correctly.

Previously I was concerned that the FPGA bank was 3.3V with ADC SPI expecting 1.8V signals.

I was able to read back the register values correctly. I changed several time to make certain. And the correct register values were read everytime.

Having said this, I'm trying the following

Send a test pattern from ADC32J25 and verify in the FPGA.
- I was using several registers: 3Bh, 09h, 0Ah, and 0Bh.
- I think 09h, 0Ah, and 0Bh are generating the test pattern at the SERDES level
- 3Bh is generating at the Link Layer
- In the end, I was just using 3Bh to try the different test patterns
- I have gotten to a point where when I set the pattern to K28.5 (010) I was capturing BCBC on consistent basis
- However, for other patterns, the captured data was not consistent
- The SYSREF would be periodic. Do I need to make this one time to be able to capture ADC data?

Fullscreen ADC_regi.txt Download

Would it be possible for you to take a look at the registers and let me know where I need to make changes to receive consistent test patterns?

If possible, could you provide a few sets of registers values with expected received data patterns?

Also let me know if I need to make changes to LMK04828 to make the SYSREF one time.

Btw

Frames per multi frame: 20
Octets per frame: 2
Scrambling: off

Besides 3Bh, 09h, 0Ah, and 0Bh, there is also 2Ah for Serdes test pattern. I'm trying to see which test modes I should be looking at.

In terms of setting the JESD204B on the FPGA

Scrambling: disabled
0 = No SYSREF event is required on a Link Re-Sync event:
- RX core deasserts SYNC on the next LMFC.
- SYSREF delay: 0 core_clk cycles delay
- 0 = Core only aligns LMFC counter on the first SYSREF event detected following reset,
  and ignores subsequent SYSREF events

Thanks again for your help

Andrew

0 Andrea Vallenilla over 2 years ago in reply to Andrew Baek

TI__Genius 10995 points

Hello Andrew,

Why do you need to generate the test patterns? What are you trying to achieve with them? Ideally, if I know your goal/what you're trying to do with the ADC32J25, I can better support with this question. Thanks!

Best,

Andrea

0 Andrew Baek over 2 years ago in reply to Andrea Vallenilla

Intellectual 915 points

HI Andrea,

I just wanted to make certain the JESD is working properly for troubleshooting purpose but the end goal is to get the sampled data from the ADC32J25.

We can try the ADC data first.

Thank you,

Andrew

0 Andrea Vallenilla over 2 years ago in reply to Andrew Baek

TI__Genius 10995 points

Hello Andrew,

It would be great if you could test the data right away and if not we'll go back to your test pattern. If that works for you, let me know if it works/doesn't work and we can go from there.

Thanks again,

Andrea

0 Andrew Baek over 2 years ago in reply to Andrea Vallenilla

Intellectual 915 points

Hi Andrea,

Okay. Let me try it today.

Thank you,

Andrew

0 Andrew Baek over 2 years ago in reply to Andrew Baek

Intellectual 915 points

HI Andrea.

Here are a couple of screen captures to show the K characters

Also attached is a list of the register values. The only non-zero values are 2B, 30, and 31.

Not certain what the next step should be. We have reworked the FPGA design and it seems to be okay. All the clocks are working. The ILAs are working.

Regards,

Andrew

adc_regi.pdf

0 Chase W over 2 years ago in reply to Andrew Baek

TI__Mastermind 23860 points

Andrew,

This looks like sync is having issues, likely due to the format of which it was designed in. I think you will have to use the device's software sync to initialize this link. Refer to register 0x3A SYNC_REQ and SYNC_REQ_EN.

Regards, Chase

0 Andrew Baek over 2 years ago in reply to Chase W

Intellectual 915 points

Hi Chase,

You were correct.

We worked on the sync sequence and timing, and it looks like we are receiving valid data.

Please see the attached screen captures.

We just need to parse the data and verify.

One question, would it be more advantageous to have a one-time SYSREF as opposed to repeating?

I can look at but appreciate if you point me in the direction to update the LMK04828 registers for one-time SYSREF,

Regards,

Andrew

0 Chase W over 2 years ago in reply to Andrew Baek

TI__Mastermind 23860 points

Hi Andrew,

Glad you are receiving proper data now. Regarding sysref, continuous sysref is convenient but not necessary. Andrea Vallenilla , can you help with LMK reg updates?

Regards, Chase

0 Andrea Vallenilla over 2 years ago in reply to Chase W

TI__Genius 10995 points

Hello Andrew,

To just generate a pulse for your SYSREF after toggling SYNC, all you need to do is set register 0x139[1:0] = 0 (make SYSREF_MUX = Normal SYNC). Hope this helps!

Best,

Andrea

0 Andrew Baek over 2 years ago in reply to Andrea Vallenilla

Intellectual 915 points

Hi Andrea,

Attached is a waveform captured in the FPGA.

The 1st figure is a plot of the data directly from Vivado ILA.

In the 2nd, I extracted the red parts of the 1st waveform and concatenated them.

In short, I believe the basic mechanisms of the ADC and JESD are working.

We would just need to improve the synchronization process and figure out the data formatting.

So I am closing the case.

Once we get everything working as we would like to be, I may update the schematic and share for review.

Thank you and others for all the support.

Regards,

Andrewadc_capture1.pdf

0 Chase W over 2 years ago in reply to Andrew Baek

TI__Mastermind 23860 points

Hi Andrew,

I am glad to hear your link is up. The data you attached looks good! If you have any issues, please include a link to this thread in any future forum post regarding this topic as it will help to provide some backstory.

Regards, Chase

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ADC32J25: JESD204B Configuration