ADC32RF42: Lane usage

In addition to above question, I mapped the 64 bit rx_tdata accordingly and obtain 128 bit data every 2 core clk cycles as follows:

0000S9S8S7S6S5S4S3S2S1S0 where SX is 12 bit Xth sample. However it looks like I am missing 10 sample values every 2 core clk cycles in 12 bit ramp mode. For example when I get 0000S9---S0 in one clk I get 0000S29----S20 in other clk, i.e samples S19---S10 are missing. I am quite sure I do the mapping correctly. Why do you think I am missing some samples, is it something the ADC does in 12 bit ramp mode?

Hi Erdal,

The 12-bit mode is LMFS=42810. 2 lanes are used for channel A, 2 lanes are used for channel B. The ADC does not do anything differently in this mode, so I would think the mapping to 128 bit frame will contain the issue. A 64 bit frame (LMFS=42810) for this mode looks as below:

Lane DA0: S0, S1, S2, S3, S4, 0000
Lane DA1: S5, S6, S7, S8, S9, 0000

Lane DB0: S0, S1, S2, S3, S4, 0000
Lane DB1: S5, S6, S7, S8, S9, 0000

After swapping to format your JESD IP outputs, each frame of data should look like this: 

Lane DA0: 0000, S4, S3, S2, S1, S0
Lane DA1: 0000, S9, S8, S7, S6, S5

Lane DB0: 0000, S4, S3, S2, S1, S0
Lane DB1: 0000, S9, S8, S7, S6, S5

Can you share the RTL for how you map 1 core clock's worth of data (1 frame) to a 128-bit frame (2 core clocks worth of data)?

Thanks, Chase

Hi,

First of all let me mention that chB is powered down since I don't use it and I hope I don't need 2 lanes of CHB in addition to 2 lanes of CHA for a complete set of output. I am sending the RTL code of my simple data mapper below. By the way sync is always high, i.e. FPGA and ADC are always in sync and I am not gettin any frame errors.

entity data_mapper is
Port (
        rx_core_clk  : in std_logic;
        rx_tdata       : in std_logic_vector(63 downto 0);
        rx_tvalid       : in std_logic;

        mapped_data_out   : out std_logic_vector(127 downto 0);
        mapped_data_valid : out std_logic

);
end data_mapper;

architecture Behavioral of data_mapper is

signal rx_data_prev: std_logic_vector(63 downto 0);
signal toggle: std_logic:='0';

begin

mapped_data_out(127 downto 120) <= x"00";

process(rx_core_clk)
begin
       if rising_edge(rx_core_clk) then
            if (rx_tvalid='1')then
                 toggle <= not(toggle);
                 if toggle='1' then
                    mapped_data_valid <= '1';

                    --lane 0 in table 14 on page 40 of adc32rf42 datasheet, data arrives from left to right
                    mapped_data_out(11 downto 0)   <= rx_data_prev(7 downto 0) & rx_data_prev(15 downto 12);
                    mapped_data_out(23 downto 12) <= rx_data_prev(11 downto 8) & rx_data_prev(23 downto 16);
                    mapped_data_out(35 downto 24) <= rx_data_prev(31 downto 24) & rx_tdata(7 downto 4);
                    mapped_data_out(47 downto 36) <= rx_tdata(3 downto 0) & rx_tdata(15 downto 8);
                    mapped_data_out(59 downto 48) <= rx_tdata(23 downto 16) & rx_tdata(31 downto 28);

                    --lane 1
                    mapped_data_out(71 downto 60)     <= rx_data_prev(39 downto 32) & rx_data_prev(47 downto 44);
                    mapped_data_out(83 downto 72)     <= rx_data_prev(43 downto 40) & rx_data_prev(55 downto 48);
                    mapped_data_out(95 downto 84)     <= rx_data_prev(63 downto 56) & rx_tdata(39 downto 36);
                    mapped_data_out(107 downto 96)   <= rx_tdata(35 downto 32) & rx_tdata(47 downto 40);
                    mapped_data_out(119 downto 108) <= rx_tdata(55 downto 48) & rx_tdata(63 downto 60);

                 else
                    mapped_data_valid <= '0';
                    rx_data_prev <= rx_tdata;
                 end if;
            else
                 mapped_data_valid <= '0';
                 toggle <= '0';
            end if;
       end if;
end process;

end Behavioral;

I just happened to come accross the thread in the following link:

https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/698658/adc32rf42evm-is-there-any-problem-with-jesd204b-interface?tisearch=e2e-sitesearch&keymatch=adc32rf42#

on the bottom of the page they say it is possible to run ADC32RF42 at 1.5GHz 12 bit with lane rate of 8Gb/s per lane with all four lanes being actively used? Is it correct? How is this rate calculated? For this sampling mode dont we need a total bit rate of = 1.5*(64/5)(10/8)=24Gb/s. And since we can only use 2 lanes for bypass mode lane rate would be 24/2=12 Gb/s.

I hope you are not out of answers :).

Hi Erdal,

My apologies, I have just returned from being out of office. I will look at this for you today.

Thanks, Chase

Hi Erdal, please see my comments below.

Erdal G said:

Why do you think I am missing some samples, is it something the ADC does in 12 bit ramp mode?

The ADC does not do anything differently in this mode. The issue is not that you are missing samples, but rather that the FPGA is skipping every other multi-frame's worth of data. If you can pass the raw rx_data into an ILA, it might be easier to notice what is going on here potentially. When the samples are "skipped", you are meaning that the place is not padded with 0's or anything, right? The next available data that appears as rx_data is from the next multiframe?

Erdal G said:

I am sending the RTL code of my simple data mapper below.

Thank you for providing this. I myself am not fluent in HDL but I will work with our team to check if there is anything which may be causing this issue going on in the mapping.

Erdal G said:

on the bottom of the page they say it is possible to run ADC32RF42 at 1.5GHz 12 bit with lane rate of 8Gb/s per lane with all four lanes being actively used? Is it correct?

No, this linked post is not correct. I am not sure how Jim came up with 8Gbps. My guess is he used 1GSPS instead of 1.5GSPS but he did type 1.5GSPS in the thread... Either way, the calculation which you provided is correct. If sampling with just one channel at 1.5GSPS, the total throughput will be 24Gbps so across 2 lanes, each serdes lane rate will be 12Gbps.

Erdal G said:

I hope you are not out of answers :).

Never! :)

Thanks for being patient!

Regards, Chase

Hi Erdal,

Are you capable of monitoring rx_tvalid to see if it goes low at any time? Where does this signal come from? The Xilinx JESD IP? What is the frequency of rx_core_clk?

Thanks

Thanks for the response. I monitored both rx_tvalid and rx_tdata and made sure that rx_tvalid never went low. The sampling clock of the ila montoring rx_tvalid and rx_tdata was rx_core_clk, which ran at 200MHz. rx_tvalid, rx_tdata came out of the jesd IP core. The thing is that I had ADC32RF42 replaced with ADC32RF45(since ADC32RF42 and ADC32RF45 are pin compatible) on the board and ADC32RF45 works just fine, sampling at 1.5GHz with all 4 lanes working at 6Gb/s. I am telling you this because I won't be able to take any more measures :(. If you have any thoughts on why I was missing some multiframes please feel free to post answers; otherwise we can close the ticket and leave it as a mystery :).

Hi Erdal,

Thanks for the message. With that, I think we can probably consider the thread closed since you've got an immediate solution. I would however like to know if you are using the same 12-bit mode with the ADC32RF45 so I can add this to a list of items to pursue if I ever get free time. The only difference between ADC32RF42 and ADC32RF45 that I am aware is the sample rate limitation and then trim settings which optimize the performance at the different sample rates.

Thanks, Chase