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TSW14J57EVM: ADC evaluation platforms question

Ryan Crowell
Prodigy 20 points

Part Number: TSW14J57EVM

Hi everyone, 

We would like to evaluate a few of TI's multi-channel, high-speed ADCs.  It seems that TI has at least two evaluation platforms, depending upon the specific ADC to be tested, the TSW14J57EVM and the TSW1400EVM.  (There may be more platforms as well, but those were the first two I came across.)  It looks like both of those platforms are driven by the same PC software, the High Speed Data Converter Pro GUI.

In evaluating ADCs for our application, we will need to be able to "self-trigger" data captures based upon a preprogrammed threshold.  In other words, when one of the analog channels exceeds a predetermined voltage threshold, it should trigger a data collection from all available channels, hopefully including pre-trigger samples as well.  From what I found online, I could not tell if the evaluation platforms, including the PC software, support this type of triggering.  Is this possible?

Thanks so much for any help!

Ryan

  • 0
    TI__Mastermind 24550 points

    Hi Ryan,

    Inherently, this type of trigger is not supported out of the box. Our trigger is simply a 1.8V CMOS input, and upon rising transition in the FPGA will store the ADC channel data. What you are asking about may be possible if you can buffer the incoming signal using a comparator set to 1.8V output. This would achieve the type of triggering you are wanting.

    Regards, Chase 

  • 0 in reply to Chase W
    Prodigy 20 points

    Thanks Chase.  That's unfortunate - I would have guessed this would be a pretty commonly desired feature, and it would also be pretty easy to implement in the FPGA.  Oh well.  

    Thanks,

    Ryan