Other Parts Discussed in Thread: LMK04828, , TSW14J57EVM
Hi team,
The ADC model is ADC12DJ3200 and the PLL is LMK04828.
The ADC sampling rate is 5 GSPS, the sampling clock provides 2.5 GSPS, and the sysref is 3.90625 MHz, in pulse mode.
Transmitting 8 pulses at a time, the device clk to the JESD204B receiving core of the FPGA is 250MHz, and each clock is measured with an oscilloscope and a spectrum meter, and the frequency and power are as good as required. When configured, after sending the PLL_sync signal, no sync signal from the 204B receiving core was measured to the transmitting core, resulting in 204b link establishment not possible.
Could you help check this case? Thanks.
Best Regards,
Cherry
