ADS117L11: clock selection for adc

Hello Liping,

1) In datasheet, it defines 25.6MHz is typical clock input. So I use 24MHz should be fine, right?

Yes, 24MHz will work well; this is the default frequency used on the ADS127L11 evaluation board.  Note that all data rates will scale with the input frequency.  Assuming you are using OSR32, the data rate will be 400ksps when using a 25.6MHz oscillator.  When using 24MHz, the data rate will reduce by a factor of 24/25.6, or 375ksps with f-CLK=24MHz.

2) What's the ppm required of clock input?

This depends on your system requirements.  The data rate is directly proportional to the clock frequency, and any frequency measurements, or FFT analysis, will be effected by the accuracy of the clock.  The evaluation board uses a 100ppm oscillator, but your requirements may be more stringent.

3) What's amplitude required? I suppose it should follow digtital IO VDD, right?

Yes, that is correct.  The clock amplitude should be CMOS level (0V to IOVDD), and meet the below datasheet specification.

4) For jitter requirement, I think belwo should be enough for input 1MHz analog, right?

This depends on the OSR setting and the maximum input frequency that will be captured.  The equation for jitter related noise is:

SNR-jitter=20*log(2*pi*f-in*t-jitter)+10*log(OSR).

SNR is the jitter limited SNR, which should be 10dB or greater than the target SNR for the filter setting.

f-in is the maximum input frequency that will be sampled.

t-jitter is the clock jitter

OSR is the Over-sampling Ratio of the ADC digital filter.

As an example, for the ADS117L11, the SNR for most ranges is limited by the quantization noise, and can be calculated as SQNR (dB) = 6.02 × N + 1.76. For a 16-bit ADC, the SQNR is 98.1 dB.  Adding 10dB to this number is the target SNR-jitter  that is needed, or 108.1dB.  Assuming you are using the OSR=32 setting and will be sampling a 100kHz sinewave, we can back calculate the maximum allowed clock jitter.

SNR-jitter=20*log(2*pi*f-in*t-jitter)+10*log(OSR)

108.1 = 20*log(2*pi*100000*t-jitter)+10*log(32)

Solving for t-jitter:= 21.7ps-rms.

The below oscillator specs are t-jitter maximum of 1ps, so this clock oscillator will work well for all OSR settings and input frequencies for the ADS117L11.

5) use 1 oscillator + lmk1c1104 to drive 4 ADS117L11 to work, what's the in serial resistor value for adding in clock line?

If the oscillator and LMK1C1104 are in close proximity (less than 100mm) to the 4 ADS117L11 ADCs, then you do not typically need impedance matching of the clock lines.  In this case, we typically add a 10Ohm resistor in series to help attenuate ringing, but this will depend on your specific board layout and the distance between the oscillator, LMK, and ADCs. 

6) In datasheet mentioned internal clock is not for ac measurement.

This statement is provided because the internal oscillator has too much timing jitter to be used with input signals of frequency greater than 10-100Hz range.

Does ac mean the input signal coupled by capacitor?

This refers to the input signal, which can be either AC coupled or DC coupled.  If you are capturing Dynamic input signals, such as sinewaves generated by an accelerometer or some other vibration sensor, then we refer to this as AC signals.  If you are trying to capture 'DC' or slow moving signals, such as temperature measurements, then the internal oscillator can be used.

Or mean any frequent changed signal even coupled directly by resistor devider?  

Yes, the input can be an AC waveform that is DC coupled, for example, from a resistor divider

You mentioned a 1MHz analog input in one of your questions.  Please note that the ADS117L11 uses an internal filter which limits the maximum usable bandwidth of the ADC, and depends on the clock frequency and the OSR setting.  The maximum usable input frequency for the wideband filter is about 165kHz, and the SINC filter is about 243kHz.

Regards,
Keith Nicholas
Precision ADC Applications