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Synchronization of two DACs 348x

donia elotamni
Prodigy 60 points
Other Parts Discussed in Thread: DAC3484, DAC3482, DAC34H84

Hello,

I'm working on a synchronisation of two TI DACs with a module generator pattern TSW3100 and i have few questions:

I have choose the TSW3100comm_signal_pattern to generate an WCDMA-TM1 signal,  on the TSW3100 control panel: 

 - The TSW3100 includes the ability to synchronize multiple boards using a master/slave synchronization, witch mode should i use for the best results and why?

- with LVDS mode the data are always interleaved, but the connection between FPGA and DAC348x  provides 16 LVDS differential data bits, is it necessary to choose this mode if the connection is allready done?

 

on the software DAC348x_GUI_V3p3, in input format panel how can i choose between Input data: 16bit single mode or 8 bit dual mode? how and why i choose one or another?

  • 0
    TI__Guru* 79304 points

    Donia,

    Unfortunately, the current DAC348x EVMs and the TSW3100 evaluation platform do not support multi-DAC synchronization. In order to support synchronization, the OSTR signals have to be phase matched from the same CDC source. The DAC3484 EVM currently does not have the option to hook up OSTR signal externally, and you may need to modify the board in order to connect external OSTR signals. Keep in mind the OSTR signals to the two or more DACs have to be phase matched, and also need to have phase relationship with the multiple DACCLKs.

    We are planning our future EVMs with better support for multi-DAC synchronization, so please stay tuned for our upcoming EVM release.

     

    Currently, the TSW3100 would support 16bit LVDS Word Wide mode input for both the DAC3484 and DAC3482. The 8-bit byte wide interface mode is not supported. The GUI shows the functionality in case you are connecting a FPGA to the DAC EVM and need the support for 8-bit byte wide interface. 

    On the TSW3100 GUI, the "LVDS" output option is for the DAC3482 (or the DAC34H84). The I/Q data from the TSW3100 is in DDR fashion, where I is latched in on the rising edge of DATACLK and Q is latched in on the falling edge of DATACLK. 

    The "16B QDAC" output option is for the DAC3484 mode. The A/B/C/D data from the TSW3100 is also in DDR fashion, but A data and C data are latched in on the rising edge of the DATACLK, and B and D data are latched in on the falling edge of DATACLK. 

    -KH