• State TI Thinks Resolved
  • Locked Locked
  • Replies 9 replies
  • Answers 3 answers
  • Subscribers 46 subscribers
  • Views 608 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC38J84: spurs issues

Amy Luo
Expert 6895 points
Part Number: DAC38J84


Hi team,

One of our customer's issues, I translated it into English as follows, could you please provide some troubleshooting suggestions?

During the DAC38J84 test, there were spurs and harmonics, and the magnitude of the spurs affected the SFDR. Currently, three IF point frequency signals of 60/50/70MHz are output. Scattered points will appear in these frequency points. Through extensive testing, these stray points have a certain regularity. The following figure shows the point at -20MHz frequency offset when outputting at 60M, with a frequency of 40MHz. If the span is set to 200MHz, other harmonics and stray points will be seen. The point that has an impact when outputting at 60M in the following figure is 40M, which has an impact on SFDR exceeding 10dB. Other stray and harmonic signals are far away from the signal, with small amplitudes and little impact. Currently, the main need is to address the stray points at the 20M frequency offset.

                                   span 50MHZ

                                         span 200MHZ

The results of measuring multiple frequency points are as follows: （unit: MHZ）

DDS 200Mhz, signal 12.5Mhz

The first column of the table corresponds to the red font I translated.

testing environment

The FPGA outputs a DDS signal with a sampling rate of 200Mhz and a signal of 12.5M. It is fed to the DAC through the 204B interface, and after 4 times interpolation, the DAC is mixed with the internal NCO of the DAC. The mixing uses 800MHz sampling output, and the actual environment is shown in the following figure:

DDS: sampling rate 200 MHZ, signal 12.5MHZ

DAC NCO: see table above

DAC part, DAC38J84

Currently, interpolation filtering, NCO, and QMC are used, while other functions are bypassed

FPGA uses an IP core to generate DDS signals, with a sampling rate of 200M and a signal of 12.5M

Analysis Steps

1. After changing the NCO of DAC and mixing with the 12.5M signal generated by DDS, the stray points will follow the output changes, as shown in the table above

2. Change FPGA DDS=15.625M, NCO=72.5M, and the test results are as follows:

3. DDS output DC component, NCO=72.5M

I am not familiar with DAC38J84. Could you please provide some guidance on problem-solving for this customer

Best Regards,

Amy Luo

  • 0
    TI__Genius 15321 points

    Hi Amy,

    I will check on this and get back to you.

    Regards, Amy

  • 0 in reply to Amy
    TI__Genius 15321 points

    Hi Amy,

    I set this up in the lab and I saw a similar 40 MHz spur with a 60 MHz tone. However, the SFDR was much closer to datasheet spec.

    Can you send your frontend schematic for us to review?

    Regards, Amy

  • 0 in reply to Amy
    TI__Expert 6895 points

    Hi Amy,

    Thanks for looking into.  Please find the attachment.

    PCB and SCH.docx

    Did you use the EVM board for the above test? The reason for asking this question is because this customer wants the schematic, PCB, and DAC register configuration of the above test results. Could you please provide these?

    Best Regards,

    Amy

  • 0 in reply to Amy Luo
    TI__Genius 15321 points

    Hi Amy,

    I did use the custom TI DAC38J84EVM. I have attached the configuration file with the register writes used for the test. To sample at 800 MHz, the external clocking option was used. 

    I reviewed the customer's schematic, and it looks in-line with the TI recommendations.

    The schematic and PCB design can be downloaded here under 'Technical Documentation' it's the link next to 'Design Guide': 

    https://www.ti.com/tool/DAC38J84EVM 

    Regards, Amy


    DAC34J84EVM_Config.cfg

  • 0 in reply to Amy
    TI__Expert 6895 points

    Hi Amy,

    Thanks for taking the time to respond, really appreciated!

    Amy said:
    I set this up in the lab and I saw a similar 40 MHz spur with a 60 MHz tone. However, the SFDR was much closer to datasheet spec.

    The customer asked what is the dB of your test result? Could you please provide a screenshot of the test result?

    Regards,

    Amy

  • 0 in reply to Amy Luo
    TI__Genius 15321 points

    Hi Amy,

    Here is the spectrum analyzer result. We would recommend changing register 0x3 (coarse DAC gain) and / or register 0x26 (Dither enable) to see if you observe any improvement in the spur. 

    Regards, Amy

  • 0 in reply to Amy
    TI__Expert 6895 points

    Hi Amy,

    Thank you for your support over this time. The following is customer feedback:

    With this figure, the SFDR is actually only 74.23dB, and I actually measured close to this value, because the manual does not clearly identify how much a better SFDR can be achieved under this condition. According to the front, is this value the best state of the chip itself under this condition?

    In addition, by changing register 0x3 (coarse DAC gain), the spur point decreases as the signal power decreases. If the signal power is reduced by 8dB, the measured spur point is also reduced by about 8dB, but the SFDR does not change. The register 0x26 (Dither enable) does not improve the quality of the output, do you test the improvement? How much dB can be improved?

    In addition to the methods mentioned above, what other methods can be used to optimize performance?

    Regards,

    Amy

  • 0 in reply to Amy Luo
    TI__Genius 15321 points

    Hi Amy,

    Let me set this up in the lab again to retest. I will get back with you soon.

    Thanks, Amy

  • 0 in reply to Amy
    TI__Genius 15321 points

    Hi Amy,

    After re-reading this again, the SFDR value of 74.23 dB was measured on our EVM. The device was not characterized under the exact conditions you are using. However, looking at page 13 in the datasheet you can extrapolate that a SFDR of 74.23 dB would fall in line with the device characterization specs.

    Regards, Amy