Part Number: VSP5612
Helllo TI,
Some questions arise when I went through the datasheet of VSP561x. I wish you could help me to understand those contexts.
Q1. When the 4-bit CMOS output mode is chosen the 12-bit format(on Page 67), are those lower bits, i.e. bit3 to bit0, discarded?
Q2. The 12-bit format in 4-bit CMOS mode was not mentions in Table 15(on Page 68). Is this format implemented? If yes, where can the similar table be found?
Q3. Some parameters were defined twice with different meaning. Which one should a user take?
For example,
On page 141, the double interpretations on bit 9 at address 3.
On page 143,the double interpretations on bit0-bit15 at address 5.
Q4. Still, the chart of address=5,the figure above, is “(GPIO_SEL=”0”)” a typo? According to the definition of Reg Add 4, GPIO_SEL should be an output port before a output content is selected.
Q5. Is Analog Input Channel standby setting(RegAdd=2) interlocked with channel selection(RegAdd=16)?
Should Ain1 and Ain 3 are selected while one of them is set to be in standby mode?
Q6. On page141 the bit3 of RegAdd3, is the “LVDS output x2 mode” is another name of “Double Data Output in LVDS”?
Best Regards！
Wallace
